Digital Equipment Corporation

Hewlett-packard Development Company, L.p.

Compaq Computer Corporation, Inc.

Barry A Maskas

Kurt M Thaller

Nitin Dhiroobhai Godiwala

Jeffrey A Metzger

Paul M Goodwin

Jesse B Lipcon

Donald W Smelser

David A Tatosian

Siamack Ayandeh

David K Morgan

George Jerry Harris

Shilin Zhang

An example of flow control transmission can comprise receiving a transmission instruction at a transmitter. Data can be sent from the transmitter at a rate of transmission based on the transmission instruction. A rate of transmission can be monitored over a time interval to determine a difference between a minimum rate of transmission and the monitored rate of transmission over the time interval. The transmission instruction can be overridden and data released to maintain the minimum rate of transmission based on the monitored difference.

Flow control transmission

A bus interface is partitionable into at least two slices. Each slice interfaces a respective subset of data from a computer device to a system bus. Each slice also receives a corresponding subset of control information and a complete set of address information from the computer device. Moreover, each slice may be implemented on a single integrated circuit chip, which thus handles both data and control functions.

Bus interface slicing mechanism allowing for a control/data path slice

Bus interface slicing mechanism allowing for a control/data-path slice

The present invention is directed to a method of managing a cache upon detection of an address TAG parity error, The cache includes a plurality of entries for storage of data, with each entry having a corresponding address TAG entry. The method includes the steps of performing a TAG parity check for each access to the cache, and upon detection of a parity error in an address TAG, disabling allocation of TAG entries for storage of new address TAGs. A signal indicating the TAG parity error is transmitted to an error correction mechanism.

Fault management scheme for a cache memory

The present invention is directed to a method for arbitrating for control of a bus in a multiprocessor system. The multiprocessor system comprises a plurality of processors and a main memory coupled to one another by the bus, each processor including a cache memory accessible by the corresponding processor and in connection with transactions on the bus. The method includes the steps of generating requests for control of the bus and granting control of the bus in respect of one of the requests. The bus is monitored for preselected transaction activity on the bus; and an idle cycle is inserted on the bus upon monitoring the preselected transaction activity.

Intelligent snoopy bus arbiter

The present invention is directed to a method and apparatus for performing exchange transactions between caches and a main memory of a computer system, the caches and main memory being coupled to one another by a bus. The method includes the steps of providing caches of different sizes with a cache having a smallest size, and with each cache having an index fixed as a function of the size of the cache. For each exchange transaction, the number of bits of an index used to address a selected cache location are determined, and the upper bits of a memory address from a tag store location corresponding to the selected cache location are retrieved, where the retrieved upper address bits form an exchange address. In the event that the index of the selected cache location comprises more bits than the index of the cache having the fewest addressable locations, the excess bits of the index of the selected cache location are appended to the exchange address. The cache then transmits the exchange address, a memory read address, and exchange data to memory.

Method and apparatus for forming an exchange address for a system with

The present invention is directed to a computer apparatus for use in a multiprocessor computer system having a main memory storing a plurality of data items and being coupled to a bus. The bus is operated according to a SNOOPY protocol. The computer apparatus includes a processor and a cache memory coupled to the processor. The cache memory contains a subset of the data items stored in the main memory, for access by the processor and includes a TAG store comprising a plurality of VALID indicators, one VALID indicator for each of the data items currently contained in the cache memory. A bus interface is coupled to the cache memory and is adapted for coupling to the bus. The interface operates according to the SNOOPY protocol to monitor transactions on the bus for write transactions affecting data items of the subset having set VALID indicators and determines the identity of each initiator of a write transaction on the bus affecting a VALID data item of the subset. The interface operates further to invalidate or update each VALID data item of the subset when there is a write transaction affecting the data item. An invalidate operation includes a clearing of the corresponding VALID indicator for the affected data item by the interface and an update operation includes overwriting of the affected data item by the interface from the write transaction on the bus. The operation of the interface to invalidate or update is performed as a function of the identity of the initiator of the write transaction determined by the interface.

Update vs. invalidate policy for a snoopy bus protocol

A radial clock distribution system that converts a standard bus clock signal into two pairs of inverted and non-inverted clocking signals. The two pairs of clocking signals have a lower frequency, have a different phase, and are shifted one clock period apart. The clocking signals are transferred over a first set of signal lines of equal length and impedance to computing systems components that are connected to a synchronous bus. Each component includes at least one clock repeater chip to convert the clocking signals (e.g., change these signals to a 5 volt CMOS level) to a different format. The converted clocking signals are then transferred over a second set of signal lines of equal length and impedance to the gate arrays. The gate arrays includes direct drive circuitry that receives the converted clocking signals and transmits these signals to internal driver circuitry. These signals are transferred over low skew lines. The output of the interval driver circuitry is input to local buffer circuitry that distributes the converted clocking signals to elements of a component for use as clocking signals.

System for radial clock distribution and skew regulation for synchronous

A read buffering system employs a bank of FIFOs to hold sequential read data for a number of data streams being fetched by a computer. The FIFOs are located in the memory controller, so the system bus is not used in memory accesses used to fill the stream buffer. The system stores addresses used for read requests made by a CPU, and if a next sequential address is then detected in a subsequent read request, this is designated to be a stream (i.e., sequential reads). When a stream is thus detected, data is fetched from DRAM memory for addresses following the sequential address, and this prefetched data is stored in one of the FIFOs. The system also prevents the unnecessary prefetching of data by preventing certain CPU requests from being used to detect streams. A FIFO is selected using a least-recently-used algorithm. When the CPU subsequently makes a read request for data in a FIFO, this data can be returned without making a memory access. By taking advantage of page mode, access to the DRAM memory for the prefetch operations can be transparent to the CPU, resulting in substantial performance improvement if sequential accesses are frequent. The data is stored in the DRAMs with ECC check bits, and error detection and correction (EDC) is performed on the read data downstream of the stream buffer, so the stream buffer is protected by EDC.

History buffer control to reduce unnecessary allocations in a memory

A computer system including a plurality of processors and a bus coupling the processors to one another via respective bus interfaces. The bus includes a plurality of slots for coupling the interfaces to the bus. Each interface includes an ID register coupled to the interface device, the ID register containing identification information unique to the slot of the bus used to couple the respective interface to the bus. The interface device is responsive to an address command cycle of the bus to place the identification information from the ID register on the bus during a READ bus transaction initiated by the interface and directed to another slot of the bus. A processor requiring identification of the corresponding slot causes the respective interface to initiate a READ bus transaction directed to another slot of the bus. The bus is operated so that the module at the slot to which the READ transaction is directed, returns the slot identification information to the initiator interface for communication to the corresponding processor.

Processor identification mechanism for a multiprocessor system

The present invention is directed to a control flow logic device for handling data received from a bus by a bus interface, in response to a bus read transaction, and transferred to a processor. The control flow logic includes an error checker to check data received from the bus for hard errors and parity errors and an ECC generator to generate an ECC for the received data, the ECC being forced to a bad ECC when a hard error is detected by the error checker and to a good ECC in the absence of a hard error. An error signal generator is utilized to generate and transmit an error signal to the processor when there is a hard error or a parity error in the received data and a data mover transmits the received data and the ECC to the processor.

Scheme for error handling in a computer system

A processor apparatus for use in a multiprocessor computer system having a main memory storing a plurality of data items and being coupled to a bus operating according of a SNOOPY protocol. The processor apparatus includes a processor, a primary cache, a backup cache and a bus interface. The backup cache memory a first TAG store comprising a plurality of VALID indicators, one VALID indicator for each of the data items currently contained in the backup cache memory. The primary cache memory includes a second TAG store comprising a plurality of address indicators and a plurality of VALID indicators, one address indicator and one VALID indicator for each of the data items currently contained in the primary cache memory. The interface includes a duplicate TAG store coupled to the primary cache memory, the duplicate TAG store consisting of a copy of the address indicators of the second TAG store. The bus interface is coupled to the processor, the backup cache memory and to the bus. The bus interface operates in accordance with a SNOOPY protocol to monitor transactions on the bus for write transactions affecting data items in the corresponding backup cache memory having set VALID indicators. The bus interface will invalidate or update each VALID data item of the backup cache memory when there is a write transaction affecting data item and assert an invalidate signal for an affected data item indicated by the address indicators of the duplicate TAG store. The invalidate signal causes the VALID indicator in the second TAG store for the affected data item to be cleared.

Duplicate tag store for a processor having primary and backup cache

The present invention is a circuit for converting the logic voltage levels from those of a first device to those of a second device. This conversion is accomplished while substantially isolating the second device from the effects of the first device that could influence the outputs of the second device that represent the converted logic level voltages.

Self-compensating voltage level shifting circuit

A digital data processing system includes a plurality of processing subsystems, each including an adapter for enabling transfers between the resident subsystem and other subsystems. The adapter includes a master section which enables transfers of data initiated by the subsystem between the input/output bus and the higher level communications mechanism, a slave section which enables transfers of data between the higher level communications mechanism and the input/output bus initiated by another subsystem and an interprocessor communications mechanism for enabling the subsystem and other subsystems to communicate to thereby enable the other subsystems to perform control operations in connection with the subsystem.

Bus adapter unit for digital processing system

A self-testing memory simultaneously writes test patterns into the memory banks of the memory, simultaneously compares the contents of one of the memory banks with the contents of the other of the banks, and records errors when the contents of the one memory bank differ from the contents of the other banks.

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Sterling, MA, United States of America

Barry A Maskas