Drexel University

Stony Brook University

Baris Taskin

Ahmet Can Sitik

Ying Teng

Kapil R Dandekar

Selcuk Kose

Jonathan Eli Spanier

Jianchao Lu

Ragh Kuttappa

Vasil Pano

Yuqiao Liu

Weicheng Liu

Ibrahim Tekin

Emre Salman

Guannan Chen

Eric M Gallo

On-chip wireless links offer improved network performance due to long distance communication, additional bandwidth, and broadcasting capabilities of antennas. A Through-Silicon Via (TSV)-based antenna design called TSV_A establishes multi-band wireless communication through the silicon substrate medium with only a 3 dB loss over a 30 mm on-chip distance. Simulation results show an improvement in network latency up to &#x2dc;13% (average improvement of &#x2dc;7%), energy-delay improvements of &#x2dc;34% on average, and an improvement in throughput up to &#x2dc;34% (average improvement).

TSV-based on-chip antennas, measurement, and evaluation

Modern integrated circuits have an increasing need for various levels of both supply voltage (V) and operating frequency (f) available at fine spatial and temporal granularity. This work introduces a solution that provides a number and quality of locally distributed V/f domains through FOPAC. Opportunistically sharing design resources and features between multi-phase voltage regulators (MPVRs) and resonant rotary clocks (ReRoCs) enabling i) the scalability to hundreds of domains, ii) fast switching times for both voltage and frequency, leading to temporal flexibility, and iii) locally distributed designs, leading to spatial flexibility.

Flexible on-chip power and clock

A system for performing slew-driven clock tree synthesis includes pair selection and cost metric definition considering physical distance for efficient sink clustering; slew and skew-aware merging point computation for routing; and slew and insertion slew-aware net splitting.

Slew-driven clock tree synthesis

A dynamic rotary traveling wave oscillator circuit includes plurality of multi-output spot-advancing blocks (MOSABs) forming a main-loop and a plurality of multi-input spot-advancing blocks (MISABs) forming a sub-loop. Depending on a desired division ratio, a connection connects blocks on the MOSABs and MISABs to create the desired division ratio.

Resonant frequency divider design methodology for dynamic frequency scaling

One aspect of the invention provides a including: (a) placing N&#xd7;N max size buffers at an (n&#x2212;1)st level of one of the voltage domains i until a maximum slew slewwithin the voltage domain i exceeds a defined slew threshold; (b) calculating maximum insertion delay values for all cases for each of the voltage domains; (c) if the maximum insertion delay values for all cases are associated with a single voltage domain j: (i) adding a max size buffer to all voltage domains except voltage domain j; and (ii) repeating steps (b) and (c); (d) reducing buffer sizes for each of the voltage domains; (e) recalculating maximum insertion delay values; and (f) adding parallel buffers to a first level of the voltage domain having a highest maximum insertion delay until the calculated skew across the plurality of voltage domains no longer improves.

Methods and computer-readable media for synthesizing a multi-corner mesh-based clock distribution network for multi-voltage domain and clock meshes and integrated circuits

Provided are multimaterial devices, such as coaxial nanowires, that effect hot photoexcited electron transfer across the interface of the materials. Modulation of the transfer rates, manifested as a large tunability of the voltage onset of negative differential resistance and of voltage-current phase, may be effected by modulating electrostatic gating, incident photon energy, and the incident photon intensity. Dynamic manipulation of this transfer rate permits the introduction and control of an adjustable phase delay within a device element.

Tunable hot-electron transfer within a nanostructure

A clock mesh network synthesis method is proposed which enables clock gating on the local sub-trees of the clock mesh network in order to reduce the clock power dissipation. Clock gating is performed with a register clustering strategy that considers both i) the similarity of switching activities between registers in a local area and ii) the timing slack on every local data path of the design area. The method encapsulates the efficient implementation of the gated local trees and activity driven register clustering with timing slack awareness for clock mesh synthesis. With gated local tree and activity driven register clustering, the switching capacitance on the mesh network can be reduced by 22% with limited skew degradation. The method has two synthesis modes as low power mode and high performance mode to serve different design purposes.

Growing community of inventors

Philadelphia, PA, United States of America

Baris Taskin