Motorola Corporation

Barbara Vasquez

Peter J Zdebel

William M Williams

Michael P Masquelier

Scott E Lindsey

Patrick F Thompson

Robert C Kane

Scott S Roth

John W Stafford

James Jen-Ho Wang

Hang M Liaw

Bernard W Boland

Christian A Seelbach

E James Prendergast

Irenee M Pages

Marlene J Begay

Patrick Thompson

Peter J Zoebel

A semiconductor wafer contact system includes a sealed bladder (32) containing incompressible material. The sealed bladder (32) presses against a flexible circuit layer (28) including an array of electrical contacts (30). The bladder (32) forces the array of electrical contacts (30) against a corresponding array of device electrical contacts (12) on die (11) of a semiconductor wafer (10). The bladder (32) adapts in shape to compensate for die level and wafer level irregularities in contact height and non-parallelism. Additionally, bladder (32) ensures a constant force between membrane contacts (30) and die contacts (12), across the entire wafer (10).

Semiconductor wafer contact system and method for contacting a

A semiconductor wafer contact system includes a base substrate (13) which has an array of raised supports (18). The array of raised supports (18) are distributed in a pattern corresponding to the pattern of electrical contacts (12) on the semiconductor wafer (10), to be contacted. In between the base substrate (13) and the wafer to be contacted (10) is a flexible circuit layer (14) including an array of electrical contacts (15) having the same pattern as the contacts (12) of the wafer and the raised supports (18). The raised supports (18) provide focused and localized force, pressing the membrane test contacts (15) against the wafer electrical contacts (12).

A board (10) for testing an integrated circuit disposed on a semiconductor wafer. The board contains a plurality of substantially parallel signal layers (14) and power planes (16) that are supported and electrically isolated by a dielectric material (12). One or more constraint layers (18,20) are disposed in the dielectric material, and the constraint layers have a coefficient of thermal expansion of about 1-6 ppm/.degree.C. In a preferred embodiment, the dielectric material is a fluoropolymer with-a ceramic or silica filler, and the constraint layers are an iron-nickel alloy of about 30-40 percent nickel by weight. The board has thermal expansion characteristics substantially similar to silicon to ensure good contact to a silicon wafer during burn-in testing.

Integrated circuit testing board having constrained thermal expansion

A multiple output, vertical MOSFET device (11) with improved electrical performance and thermal dissipation is integrated with an additional semiconductor device or semiconductor circuit (18) on a single semiconductor substrate (34). The method of making the vertical MOSFET device (11) involves thinning the semiconductor substrate (34) after fabricating the vertical MOSFET device (11) and the semiconductor circuit (18) to reduce the vertical component of electrical and thermal resistance and to increase the thermal dissipation efficiency. Electrical performance is improved by thinning the semiconductor substrate (34) and by providing a low resistivity, patterned metal buried layer. Thermal management is enhanced by using flip chip bumps (24) to dissipate heat from a top surface (31) of the semiconductor substrate (34) and by using the patterned buried metal layer (26) to dissipate heat from a bottom surface (32) of the semiconductor substrate (34).

Vertical MOSFET device having frontside and backside contacts

A system and method for aligning a semiconductor device (10) to a fixture (11) is provided. A first physical alignment feature (12) on the semiconductor device (10) and a second physical alignment (24) on the fixture (11) mate to align and hold the semiconductor device (10) in place. In one embodiment the physical alignment features (12) and (24) are produced using standard photolithography techniques, resulting in precise alignment features. In another embodiment the physical alignment features (12) and (24) are designed and placed to control the direction the thermal expansion of the semiconductor device (10) relative to the fixture (11).

Method for aligning a semiconductor device

A method for the fabrication of a trench isolation region (44) includes the deposition of first, second, and third oxidizable layers (28, 34, 42). The first oxidizable layer (28) is deposited to overlie the surface of a trench (12) formed in a semiconductor substrate (10). The first oxidizable layer (28) also fills a recess (26) formed in a masking layer (14), and resides adjacent to the upper surface of the trench (12). After oxidizing the first oxidizable layer (28), a second oxidizable layer (34) is deposited to fill the trench (12). A third oxidizable layer (42) is deposited to overlie the second oxidizable layer (34) and fills a remaining portion of the recess (26). An oxidation process is performed to oxidize oxidizable layer (42) and a portion of second oxidizable layer (34) to form a trench isolation region (44). In an alternative embodiment of the invention, a shallow isolation region (46) is formed in proximity to the trench isolation region ( 44).

Encapsulation method for localized oxidation of silicon with trench

A reduction in defects and lateral encroachment is obtained by utilizing a high pressure oxidation in conjunction with an oxidizable layer conformally deposited over an oxidation mask. The use of high pressure oxidation provides for the formation of LOCOS oxide without the formation of defects. Any native oxide present on the substrate surface is removed by using a ramped temperature deposition process to form oxidizable layer and/or a high temperature anneal is performed to remove the native oxide at the substrate surface. In this embodiment, any oxide which can act as a pipe for oxygen diffusion is removed. Therefore, nominal or no lateral encroachment is exhibited.

High-pressure polysilicon encapsulated localized oxidation of silicon

A method for forming an electron emitter layer wherein the electron emitter layer comprises a plurality of elemental conductive materials that etch at dis-similar rates to provide a structure with an edge exhibiting a geometric discontinuity of small radius of curvature.

Non-homogeneous multi-elemental electron emitter

A method for forming a field emission device. The method includes steps which utilize sidewall spacer formation techniques. The sidewall spacer(s) are employed to properly orient the various conductive elements of the field emission device.

Method for forming a field emission device

A method of forming planar isolation regions in semiconductor structures includes providing a semiconductor substrate and forming a semiconductor layer thereon. A dielectric layer comprising at least two different dielectric materials is disposed on the semiconductor layer and a trench is etched therethrough and into the semiconductor layer. Dielectric sidewalls are formed in the trench which is then filled by selectively forming depositing polycrystalline silicon therein. The semiconductor material is then at least partially oxidized to form the planar isolation region. The isolation regions disclosed herein may be used for both intradevice and interdevice isolation.

Method of forming planar isolation regions

A method is described for planarizing isolated regions (12) and active regions (22) of a semiconductor wafer (10). Semiconductor wafer (10) is provided with islands of dielectric (12) that cover portions of the semiconductor wafer (10), while leaving other portions of the semiconductor wafer (10) exposed. The dielectric islands (12) have a polysilicon layer (13) that covers the dielectric islands' (12) top surface. A blanket layer of silicon is deposited on the polysilicon layer (13) that covers the top surface of the dielectric islands and is deposited between the dielectric islands (12). Planarizing the blanket layer of epitaxial silicon is achieved by a chemical-mechanical means, thereby producing a planar surface of isolated areas (12) and active areas (22).

Method for planarizing isolated regions

A method of fabrication of a device having laterally isolated semiconductor regions. In a preferred embodiment, laterally isolated polysilicon features are created with vertical, nitride-sealed sidewalls. The nitride-sealed sidewalls formed using sidewall spacer technology eliminate oxide encroachment while further preventing the loss of dopant laterally during thermal processing. The final structure comprises polysilicon features flanked by either oxide isolation or additional polysilicon features and is planar without requiring a planarization etchback. The process is applicable to polysilicon electrodes over active areas as well as polysilicon resistors over isolation oxide.

Fabrication of devices having laterally isolated semiconductor regions

A method of fabricating a semiconductor structure having self-aligned diffused junctions is provided wherein a first dielectric layer, a doped semiconductor layer and a second dielectric layer are formed on a semiconductor substrate. An opening extending to the semiconductor substrate is then formed through these layers. Undoped semiconductor spacers are formed in the opening adjacent to the exposed ends of the doped semiconductor layer and dopant is diffused from the doped semiconductor layer through the undoped semiconductor spacers and into the semiconductor substrate to form junctions therein. This provides for integrated contacts through the doped semiconductor layer.

Method of fabricating a structure having self-aligned diffused junctions

A method of fabricating multiple trench semiconductor structures wherein a preferred embodiment includes forming an epitaxial silicon layer on a silicon substrate and a dielectric layer on the epitaxial silicon layer. An opening is then formed which extends through the dielectric layer and into the epitaxial silicon layer. Sidewall spacers are formed in the opening and an oxide lens is formed in the opening between the sidewall spacers. The sidewall spacers are then removed and trenches are formed in the opening where the sidewall spacers were formerly disposed.

Multiple trench semiconductor structure method

A method of fabricating a semiconductor structure includes forming a thermal oxide layer, a polysilicon layer and a first dielectric layer on a substrate and using a mask to form at least one opening therein. Dielectric spacers are then formed in the opening and a trench having a self-aligned reduction in width due to the dielectric spacers is etched into the substrate beneath the opening. A dielectric trench liner is then formed prior to filling the trench with polysilicon. A second mask is then used to form isolation element openings in the first dielectric layer in which shallow isolation elements are formed.

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Chandler, AZ, United States of America

Barbara Vasquez