Siemens Aktiengesellschaft

Barbara Hasler

Josef Willer

Emmerich Bertagnolli

Paul-Werner Von Basse

Bernd Goebel

Willy Beinvogl

Franz Hofmann

Hans Reisinger

Bernd Gobel

Karl-Heinz Tietgen

The SRAM cell arrangement comprises six MOS transistors per memory cell that are fashioned as vertical transistors. The MOS transistors are arranged at sidewalls of trenches (G,G,G,). Parts of the memory cell such as, for example, gate electrodes (Ga,Ga,) or conductive structures (L,) fashioned as spacer are contacted via adjacent, horizontal, conductive structures (H,) arranged above a surface (O) of a substrate (S). Connections between parts of memory cells ensue via third conductive structures (L,) arranged at the sidewalls of the depressions and word lines (W) via diffusion regions (D,) that are adjacent to the sidewalls of the depressions within the substrate (S), via first bit lines, via second bit lines (B,) or/and via conductive structures (L,L,, L,) that are partially arranged at different height with respect to an axis perpendicular to the surface (O). Contacts (K,) contact a plurality of parts of the MOS transistors simultaneously.

SRAM cell arrangement and method for manufacturing same

An SRAM cell arrangement which includes six MOS transistors per memory cell wherein each transistor is formed as a vertical transistors. The MOS transistors are arranged at sidewalls of trenches. Parts of the memory cell such as, for example, gate electrodes or conductive structures fashioned as spacers are contacted via adjacent, horizontal, conductive structures arranged above a surface of a substrate. Connections between parts of memory cells occur via third conductive structures arranged at the sidewalls of the depressions and word lines via diffusion regions that are adjacent to the sidewalls of the depressions within the substrate, via first bit lines, via second bit lines and/or via conductive structures that are partially arranged at different heights with respect to an axis perpendicular to the surface. Contacts contact a plurality of parts of the MOS transistors simultaneously.

The memory cell configuration comprises vertical transistors which are connected in a NOR architecture. The vertical transistors are disposed on flanks of trenches. Each vertical transistor includes an electrically insulated floating gate electrode, whose charge can be varied by Fowler-Nordheim tunneling due to a voltage drop between a control gate electrode and a source/drain region. The length of a coupling area in a direction parallel to a channel width, between the control gate electrode and the floating gate electrode is less than the channel width, in order to reduce the operating voltage. This is achieved by thermal oxidation of parts of the flanks of the trenches. Transistors which are adjacent in a direction transverse to the trenches share bit lines. Each bit line has a lightly doped first part and a highly doped second part. The coupling area can be enlarged even further by using a strip-shaped mask, which is extended by spacers.

Electrically programmable memory cell configuration

A method for etching a double layer semiconductor structure containing metal silicide layers or a metal silicide-polysilicon layer on a silicon substrate through a photoresist mask by means of reactive ion etching wherein dissociation and ionization of reactant gases take place in a plasma, the improvement which comprises:

Method for etching integrated semiconductor circuits containing double

Polysilicon structures down to a 1 .mu.m range on substrates containing integrated semiconductor circuits are produced by plasma etching in a plate reactor with the use of SF.sub.6 and an inert gas as the reactive gas. During this process, a semiconductor crystal wafers (4, 17) covered with a SiO.sub.2 layer (16) and a polysilicon layer (15) is provided with an etch mask (14) and positioned on a grounded electrode of the plate reactor and an etching process, which achieves a high selectivity of polysilicon (15) to SiO.sub.2 (16) and to the etch mask (14), is carried out with a HF power, P, of &lt;0.1 watt/cm.sup.2, a gas pressure, p, ranging from 60 to 120 Pa, and an electrode temperature ranging from 20.degree. to 60.degree. C. With the inventive process, large scale integrated semiconductor circuits are produced in a single stage sequence with high etching selectivity, uniform etching and a high throughput of silicon wafers.

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Stockdorf, Germany

Barbara Hasler