Promos Technologies, Inc

Mosel Vitelic Corporation

Lam Research Corporation

Barbara Haselden

John Lee

Jin-Ho Kim

Chia-Shun Hsiao

Chunchieh Huang

Kuei-Chang Tsai

Daniel Wang

Tai-Peng Lee

Yi Ding

Chung Wai Leung

Zhong Dong

Eddie Chiu

Chau Arima

In a nonvolatile memory cell with charge trapping dielectric (), the tunnel dielectric () includes chlorine adjacent to the charge trapping dielectric but no chlorine (or less chlorine) adjacent to the cell's channel region (). The chlorine adjacent to the charge trapping dielectric serves to improve the programming and/or erase speed. The low chlorine concentration adjacent to the channel region prevents chlorine from degrading the data retention. Other features are also provided.

Nonvolatile memories with tunnel dielectric with chlorine

A method for manufacturing a low temperature removable silicon dioxide hard mask for patterning and etching is provided, wherein tetra-ethyl-ortho-silane (TEOS) is used to deposit a silicon dioxide hard mask.

Use of TEOS oxides in integrated circuit fabrication processes

Improved methods of manufacturing semiconductor devices are provided to reduce dielectric loss in isolation trenches of the devices. In one example, a method of manufacturing a semiconductor device includes forming a plurality of shallow trench isolation (STI) trenches in a substrate. A tunnel oxide layer, a first conductive layer, a gate dielectric layer, and a second conductive layer are formed above the substrate. The layers are etched to delineate a plurality of stacked gate structures. In particular, the etching may include: performing a first etch of the second conductive layer, wherein at least a portion of the second conductive layer above the STI trenches remains following the first etch; and performing a second etch of the second conductive layer, wherein the remaining portion of the second conductive layer above the STI trenches and portions of the gate dielectric layer above the STI trenches are completely removed by the second etch.

Fabrication of semiconductor device exhibiting reduced dielectric loss in isolation trenches

Nonvolatile memory wordlines () are formed as sidewall spacers on sidewalls of control gate structures (). Each control gate structure may contain floating and control gates (), or some other elements. Pedestals () are formed adjacent to the control gate structures before the conductive layer () for the wordlines is deposited. The pedestals will facilitate formation of the contact openings () that will be etched in an overlying dielectric () to form contacts to the wordlines. The pedestals can be dummy structures. A pedestal can physically contact two wordlines.

Use of pedestals to fabricate contact openings

In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer (), another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion (X) of the layer adjacent to the feature to be formed by the isotropic etch. That portion is entirely or partially removed by the anisotropic etch. Then the isotropic etch mask () is formed to extend beyond the feature over the location of the portion subjected to the anisotropic etch. If that portion was removed entirely, then the isotropic etch mask may completely seal off the feature to be formed on the side of that portion, so the lateral etching will not occur. If that portion was removed only partially, then the lateral undercut will be impeded because the passage to the feature under the isotropic etch mask will be narrowed.

Use of multiple etching steps to reduce lateral etch undercut

Isotropic etching of sacrificial oxide that is adjacent to a trench fill step in an STI wafer can lead to undesired etching away of a sidewall of the trench fill material (e.g., HDP oxide). A sidewall protecting method conformably coats the trench fill step and sacrificial oxide with an etch-resistant carbohydrate. In one embodiment, conforming ARC fluid is spun-on and hardened. A selective, dry plasma etches the hardened ARC over the sacrificial oxide while leaving intact part of the ARC that adheres to the trench fill sidewall. The remnant sidewall material defines a protective shroud which delays the subsequent isotropic etchant (e.g., wet HF solution) from immediately reaching the sidewall of the trench fill material. The delay length of the shroud can be controlled by tuning the etchback recipe. In one embodiment, the percent oxygen in an Oplus Clplasma and/or bias power during the plasma etch is used as a tuning parameter.

Formation of removable shroud by anisotropic plasma etch

A method of forming a double gate structure including sidewalls of substantially similar vertical profile. One photoresist masking step is used to define the top gate, which is then used as a mask to define the bottom gate. The bottom polysilicon layer is etched by a physical and chemical process combination to form a bottom gate with vertical sidewalls substantially inline with the sidewalls of the top gate.

Formation of a double gate structure

An OXO-type inter-poly insulator (where X is a high-K metal oxide and O is an insulative oxide) is defined by forming an amorphous metal oxide layer on a silicon-based insulator (e.g., a silicon oxide layer) and then nitridating at least upper and lower sub-layers of the amorphous metal oxide with a low temperature plasma treatment that maintains temperature below the recrystallization temperature of the amorphous material. Such a plasma treatment has been found to improve breakdown voltage characteristics of the insulator. In one embodiment, the metal oxide includes aluminum oxide and it is fluorinated with low temperature plasma prior to nitridation.

Low temperature nitridation of amorphous high-K metal-oxide in inter-gates insulator stack

A method of etching nitride over oxide is provided for the formation of vertical profile nitride spacers with high uniformity while maintaining the integrity of underlying thin oxide layers. The method includes providing a first gas flow including a first fluorocarbon and a second fluorocarbon at a first ratio, applying a first quantity of power to the first gas flow to create a first plasma, etching a first portion of a silicon nitride layer with the first plasma, providing a second gas flow including the first fluorocarbon and the second fluorocarbon at a second ratio greater than the first ratio, applying a second quantity of power to the second gas flow to create a second plasma, and etching a second portion of the silicon nitride layer with the second plasma.

Two stage etching of silicon nitride to form a nitride spacer

In a nonvolatile memory, a floating gate ( ) is covered with ONO ( ), and a control gate polysilicon layer ( ) is formed on the ONO. After the control gate is patterned, the control gate sidewalls are oxidized to form a protective layer ( ) of silicon dioxide. This oxide protects the control gate polysilicon during a subsequent etch of the silicon nitride portion ( ) of the ONO. Therefore, the silicon nitride can be removed with an isotropic etch. A potential damage to the substrate isolation dielectric ( ) is therefore reduced. Other embodiments are also provided.

Sidewall protection in fabrication of integrated circuits

A method for improving profile control during an etch of a nitride layer disposed above a silicon substrate is disclosed. The nitride layer 106 is disposed below a photoresist mask 108A. The method includes positioning the substrate, including the nitride layer and the photoresist mask, in a plasma processing chamber. There is also included flowing a chlorine-containing etchant source gas into the plasma processing chamber. Further, there is included igniting a plasma out of the chlorine-containing etchant source gas to form a chlorine-based plasma within the plasma processing chamber. Additionally, there is included treating, using a chlorine-based plasma, the photoresist mask in the plasma processing chamber. The treatment of the photoresist is configured to etch at least a portion of the photoresist mask and to deposit passivation polymer on vertical sidewalls of the photoresist mask without etching through the nitride layer.

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Cupertino, CA, United States of America

Barbara Haselden