Infineon Technologies Ag

Barbara Eichinger

Martin Mischitz

Manfred Schneegans

Ingo Muri

Oliver Hellmund

Stefan Krivec

Markus Heinrici

Thorsten Meyer

Francisco Javier Santos Rodriguez

Johannes Baumgartl

Iris Moder

Rainer Pelzer

Alexander Herbrandt

Annette Saenger

Alparslan Takkac

Jacob Tillmann Ludwig

Frederik Otto

Stefan Karner

Fabian Craes

Marian Sebastian Broll

Alfred Binder

Fabien Thion

Doris Sommer

Ali Roshanghias

A method of forming a semiconductor device includes providing a carrier comprising a die attach pad, providing a semiconductor die that includes a bond pad disposed on a main surface of the semiconductor die, and providing a metal interconnect element, arranging the semiconductor die on the die attach pad such that the bond pad faces away from the die attach pad, and welding the metal interconnect element to the bond pad, wherein the bond pad comprises first and second metal layers, wherein the second metal layer is disposed between the first metal layer and a semiconductor body of the semiconductor die, wherein a thickness of the first metal layer is greater than a thickness of the second metal layer, and wherein the first metal layer has a different metal composition as the second metal layer.

High density and durable semiconductor device interconnect

A semiconductor device includes a semiconductor die, an electrical contact arranged on a surface of the semiconductor die, and a metal layer arranged on the electrical contact, wherein the metal layer includes a singulated part of at least one of a metal foil, a metal sheet, a metal leadframe, or a metal plate. When viewed in a direction perpendicular to the surface of the semiconductor die, a footprint of the electrical contact and a footprint of the metal layer are substantially congruent.

Semiconductor device including an electrical contact with a metal layer arranged thereon

A multi-chip device is provided. The multi-chip device includes a first chip, a second chip mounted on the first chip, and a hardened printed or sprayed electrically conductive material forming a sintered electrically conductive interface between the first chip and the second chip.

Multi-chip device, method of manufacturing a multi-chip device, and method of forming a metal interconnect

A semiconductor device and method for fabricating a semiconductor device, comprising a paste layer is disclosed. In one example the method comprises attaching a substrate to a carrier, wherein the substrate comprises a plurality of semiconductor dies. A layer of a paste is applied to the substrate. The layer above cutting regions of the substrate is structured. The substrate is cut along the cutting regions.

Method for fabricating a semiconductor device comprising a paste layer and semiconductor device

An integrated circuit device including a chip die having a first area with a first thickness surrounding a second area with a second thickness, the first thickness is greater than the second thickness, the chip die having a front-side and a back-side, at least one passive electrical component provided at least one of in or over the chip die in the first area on the front-side, and at least one active electrical component provided at least one of in or over the chip die in the second area on the front-side.

Monolithically integrated chip including active electrical components and passive electrical components with chip edge stabilization structures

A method of manufacturing a layer structure includes: forming a first layer over a substrate; planarizing the first layer to form a planarized surface of the first layer; and forming a second layer over the planarized surface; wherein a porosity of the first layer is greater than a porosity of the substrate and greater than a porosity of the second layer; wherein the second layer is formed by physical vapor deposition; and wherein the first layer and the second layer are formed from the same solid material.

Method of manufacturing a layer structure having partially sealed pores

A method of manufacturing an electronic device may include: forming at least one electronic component in a substrate; forming a contact pad in electrical contact with the at least one electronic component; wherein forming the contact pad includes: forming a first layer over the substrate; planarizing the first layer to form a planarized surface of the first layer; and forming a second layer over the planarized surface, wherein the second layer has a lower porosity than the first layer.

Method of manufacturing an electronic device having a contact pad with partially sealed pores

Growing community of inventors

Villach, Austria

Barbara Eichinger