International Business Machines Corporation

Barbara Ann Waterhouse

Zhong-Xiang He

Douglas Duane Coolbaugh

Vidhya Ramachandran

Wolfgang Sauter

Wagdi William Abadeer

Ebenezer E Eshun

Michael Joseph Zierak

Natalie Barbara Feilchenfeld

Bradley Alan Orner

Eric Adler

Matthew D Moon

Michael Lawrence Gautsch

Eric Jeffrey White

William Joseph Murphy

Jeffrey Alan Brigante

Stephen P Cole

An RF structure that includes an optimum padset for wire bonding and a high performance inductor that contains relatively thick metal inductor wires, both of which are located atop the final interconnect level of an interconnect structure. Specifically, the RF structure includes a dielectric layer having metal inductor wires of a first thickness and a metal bond pad having a major area of a second thickness located on a surface thereof, wherein the first thickness is greater than the second thickness. In the inventive RF structure, the majority of the metal bond pad is thinned for wire bonding, while maintaining the full metal wire thickness in the other areas of the structure for inductor performance requirements, such as, for example, low resistivity. Methods for fabricating the aforementioned RF structure are also provided.

Optimum padset for wire bonding RF technologies with high-Q inductors

Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer is formed above a lower conductor layer and an upper conductor layer is formed above the dielectric layer. The invention then forms an etch stop layer above the upper conductor layer and the dielectric layer, and forms a hardmask (silicon oxide hardmask, a silicon nitride hardmask, etc.) over the etch stop layer. Next, a photoresist is patterned above the hardmask, which allows the hardmask, the etch stop layer, the dielectric layer, and the lower conductor layer to be etched through the photoresist.

Formation of metal-insulator-metal capacitor simultaneously with aluminum metal wiring level using a hardmask

The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Line (BEOL) levels. An insulator layer is selectively formed to encapsulate at least a top plate of the MIM capacitor to protect the MIM capacitor from damage due to process steps such as, for example, reactive ion etching. By selective formation of the insulator layer on the MIM capacitor, openings in the inter-level dielectric layers are provided so that hydrogen and/or deuterium diffusion to the FETs can occur.

Non-continuous encapsulation layer for MIM capacitor

A structure and a method of forming the structure. The structure including: an integrated circuit chip having a set of wiring levels from a first wiring level to a last wiring level, each wiring level including one or more damascene, dual-damascene wires or damascene vias embedded in corresponding interlevel dielectric levels, a top surface of a last damascene or dual-damascene wire of the last wiring level substantially coplanar with a top surface of a corresponding last interlevel dielectric level; a capping layer in direct physical and electrical contact with a top surface of the last damascene or dual-damascene wire, the last damascene or dual-damascene wire comprising copper; a dielectric passivation layer formed on a top surface of the last interlevel dielectric level; and an aluminum pad in direct physical and electrical contact with the capping layer, a top surface of the aluminum pad not covered by the dielectric passivation layer.

Low cost bonding pad and method of fabricating same

A bond pad upon which a wirebond interconnection is formed, consisting of a first bond pad layer formed on a chip, and a second bond pad layer formed on the first bond pad layer, wherein the first bond pad layer is more resistant to removal than the second bond pad layer during probe testing, and the first bond pad layer increases resistance to interconnection failure during mechanical testing.

Bond pad

Non-Continuous encapsulation layer for MIM capacitor

Growing community of inventors

Richmond, VT, United States of America

Barbara Ann Waterhouse