International Business Machines Corporation

Intel Corporation

Other

Barbara A Chappell

Terry I Chappell

Stanley Everett Schuster

Bruce Martin Fleischer

Michael P Beakes

Mark T Bohr

Jerry M Woodall

Andrew W Yeoh

David J Widiger

Mark S Milshtein

Ranjith Kumar

M Clair Webb

Gary Stephen Ditlow

Barry Lee Dorfman

Vinod Narayanan

Mahmut K Ebcioglu

Sourav Chakravarty

Quan Shi

Ghavam G Shahidi

Ian A Young

Sang Hoo Dhong

Stephen M Cea

Thomas D Fletcher

Robert Alan Philhower

Thekkemadathil V Rajeevakumar

Thao Ngoc Nguyen

Rudolf Adriaan Haring

Bijan Davari

Parsotam Trikam Patel

Lewis M Terman

Yuan Taur

George A Sai-Halasz

Yeong-Chang L Lien

Priyadarsan Patra

Jeffrey Y Tang

Prashant S Sawkar

Edward Seewann

Xinning Wang

Hung-Hui Hsieh

George Anthony Sai Halasz

Phoung Kim Phan

Talal Kamel Jaber

George Anthony Halasz

Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.

Multi version library cell handling and integrated circuit structures fabricated therefrom

Through gate fin isolation for non-planar transistors in a microelectronic device, such as an integrated circuit (IC). In embodiments, ends of adjacent semiconductor fins are electrically isolated from each other with an isolation region that is self-aligned to gate electrodes of the semiconductor fins enabling higher transistor packing density and other benefits. In an embodiment, a single mask is employed to form a plurality of sacrificial placeholder stripes of a fixed pitch, a first subset of placeholder stripes is removed and isolation cuts made into the semiconductor fins in openings resulting from the first subset removal while a second subset of the placeholder stripes is replaced with gate electrodes.

Through gate fin isolation

A method and apparatus provide a digital circuit including dynamic logic that minimizes circuit-path delay, residue logic, and circuit area. The method and apparatus use a library of circuit cells to produce a digital circuit design using a mapping algorithm. The mapping algorithm firstly determines an arrangement of circuit cells to minimize the delay in the circuit design, secondly determines an arrangement of circuit cells to minimize the residue logic for the circuit design, thirdly determines an arrangement of circuit cells to minimize the circuit area for the circuit design, and then repeats the process for each node in the circuit until the best circuit design is produced in accordance with pre-determined criteria.

Method and apparatus for improving digital circuit design

A system and computer implemented method of modifying characteristics of a circuit provide enhanced performance. One embodiment of the method provides for determining a set of objective parameters for the circuit and receiving noise constraints for the circuit. Values of the objective parameters are optimized based on the noise constraints. By using noise constraints in the optimization process, a number of performance issues can be addressed.

Noise and power optimization in high performance circuits

The present invention provides a device and method for fast SRAM reading and writing. A boost voltage source is provided, wherein the boost voltage source operates to increase a conductance of a latch device in the SRAM cell relative to a conductance of an access device in the SRAM cell. By virtue of the increased relative conductance between the latch and access devices (beta ratio), the access device may be assume a wider width without jeopardizing the read stability of the cell.

VDD modulated SRAM for highly scaled, high performance cache

A dynamic incrementer, implemented in the Self Resetting Complementary Metal Oxide Semiconductor (SRCMOS) circuit family, which internally performs single rail calculations and which generates the dual rail result using a strobing technique. The carry-lookahead function is implemented with an OR tree using the complement input signals, resulting in a very fast and economical incrementer.

High performance, low power incrementer for dynamic circuits

A computer-based method automatically synthesizes, optimizes and compiles high performance control logic using SRCMOS LOGIC ARRAY MACROS, abbreviated as SLAMs. The method includes a series of steps that transform a high level design description into a set of SLAMs, and includes the steps of partitioning the logic description of a unit into blocks that are suitable for mapping to a target SLAM structure; mapping each logic partition to the target SLAM structure; creating a configuration and relative layout for the internal structure for each SLAM; creating an external description for each SLAM, each description being of sufficient detail to carry out physical design and integration of the unit which contains the SLAM; assembling the partitions implemented as SLAMs with other macros in the unit; resolving interface conflicts between the different macros by selecting appropriate signal interfaces for various SLAMs; repeatedly changing the external specifications of the various SLAMs; analyzing the performance of the unit; automatically compiling the schematic and layout of each SLAM within the unit based on the configuration and relative layout; and assembling the macros and analyzing the design for design rule violations.

Method and apparatus for synthesizing and optimizing control logic based

A logic circuit family implements self-resetting CMOS logic array macros (SLAMs) which include a plurality of inputs to which a plurality of data input signals can be applied; a plurality of input buffers coupled to receive the input signals from the inputs; a NOR circuit coupled to receive the outputs of the input buffers and a pulsed logic timing signal synchronized within a predefined window with the arrival of the data input signals; an output buffer coupled to receive the output of the NOR circuit; and an output at which a data output signal is produced, with the output signal being a logical NOR of the data input signals; and with each of the NOR circuit, the plurality of input buffers, and the output buffer optionally having a separate reset input to reset it to a standby state. The SLAMs address the very high pressure on the performance of both control logic and control logic design systems. The distinguishing features of SLAMs are uniquely combined to allow the automated design, from a logic description and interface specifications, of a complete macro satisfying predetermined design guidelines.

Compiled self-resetting CMOS logic array macros

A logic structure adapted to receive pulsed active input signals produces a logical output with a very small inherent switching delay. Pull-down transistors and complementary pull-up transistors are ratioed such that the default logical output level remains close to nominal even when the logic structure sinks or sources a DC current. When the pulsed input signals are inactive, no DC current path is enabled.

High speed ratioed CMOS logic structures for a pulsed input environment

A pulsed logic circuit test methodology and circuitry therefor are disclosed. The methodology and circuitry allow the inhibiting of reset pulses, the ability to force resets and the ability to test the circuit in a pseudo-static mode of operation.

Methodology to test pulsed logic circuits in pseudo-static mode

A method for determining an optimal design for wiring interconnect and driver power for a designed target delay begins at the floor planning stages of the chip design and may be repeated during the design process. The designer initially specifies a maximum width that wires are allowed to use and a target delay value. Then the designer gives values to weights used in the calculation of an optimization function G(d,p,w), where d is the delay, p is the power, and w is wire width. An 'ideal' slope ##EQU1## is calculated, assuming zero resistance. The designer chooses a slope decrease value from the 'ideal' slope value. For each set wire width, the delay (at the proper slope) belonging to that particular wire width is obtained. With these inputs, an optimization program according to the invention is run. This program then calculates values of the function G(d,p,w) for increasing wire pitches, starting with the minimum allowed by the technology. The process continues until (1) the target delay is set by the designer is met, (2) the largest pitch value allowed by the designer is reached, or (3) further calculation will not yield a smaller value for the optimization function.

Interconnect and driver optimization for high performance processors

A parallel self-resetting parallel binary adder provides high speed addition and subtraction. The adder combines the advantages of a fully custom design methodology with the higher performance potential of self-resetting complementary metal oxide semiconductor (CMOS) circuits. The adder logic architecture is carry look-ahead with two bit groups and requires six rows of merge logic to calculate the carry out of the Most Significant Bit (MSB). Loading on the critical path of the adder is reduced by moving as many merge blocks as possible to later rows. This allows the fan-out per stage in the critical path to be reduced from around three to two or less. The adder utilizes a bubble pipelined circuit architecture. For the adder, a bubble pipe segment consists of a row of self-resetting circuit blocks. A fast cycle time and minimum delay for each block is achieved by using fast forward amplification of the leading edge of the pulsed input signals followed by quick self-resetting of all nodes back to their standby state.

Self-resetting CMOS parallel adder with a bubble pipelined architecture,

A storage latch comprising a gate insulating layer over the substrate, shallow trenches formed through the insulating layer and in the substrate to provide device insulation; and doped regions in the substrate between the shallow trenches. The doped regions define sources and drains. Gate stacks are formed over regions of oxide adjacent the doped regions. A planarized insulator is formed between the gate stacks. Openings are provided in the planarized insulator for contacts to the doped regions and the gate stacks. Conductive material fills the openings to form contacts for the doped regions and for the gate stacks. A patterned layer of conductive material on the planarized insulator connects selected ones of the contacts for wiring portions of the latch. A six device SRAM cell comprises a deep isolation trench formed in the substrate; a first latch including two transistors formed of p-type material on a first side of the trench; a second latch including two transistors formed of n-type material on a second side of the trench opposite the first side of the trench, and connection means for electrically cross wiring the transistors of the first latch to the transistors of the second latch. In forming the latch a self-aligned process for separately forming contacts to diffusion regions and gate stacks on the semiconductor substrate is used.

SRAM cell with capacitor

A virtual multi-port RAM (VMPRAM) structure has automatic port sequencing and single-port array density and speed. VMPRAM employs input-triggered, self-resetting macros in a pipelined architecture to provide multiple self-timed on-chip cycles during one machine cycle. The VMPRAM incorporates an SRAM segmented into many input triggered, self-resetting, fast cycling blocks. A timing signal is derived from a selected SRAM block for releasing the next select signals and data to the SRAM blocks. The SRAM block inputs are only the data input bus and the decoded signals needed to select a wordline and a bitline pair, and the SRAM block cycle is only the time needed to provide adequate pulse width for word lines and bitlines. Each SRAM block, and all the circuit blocks in the path to access the SRAM blocks, are input-triggered and self-resetting. The multiple address and data input latches are multiplexed at the driver to the true and complement buses to the SRAM segments, and those buses are self-resetting. Similarly, the selected SRAM block reads data out onto a self-resetting bus, and address and data inputs are latched in blocks that are set up for the release signal by the release of the adjacent block, and these blocks are all self-resetting.

Virtual multi-port RAM employing multiple accesses during single machine

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Portland, OR, United States of America

Barbara A Chappell