Apple Inc.

Barak Baum

Eyal Gurgi

Yael Shur

Avraham Poza Meir

Micha Anholt

Naftali Sommer

Assaf Shappir

Roman Guy

Tomer Ish-Shalom

Moti Teitel

Michael Tsohar

Alex Radinski

Arik Rizel

Yoav Kasorla

Barak Rotbard

Alexander Paley

Yonathan Tate

Ronen Dar

Moshe Neerman

Etai Zaltsman

Itay Sagron

Stas Mouler

Barak Sagiv

Guy Ben-Yehuda

Einav Yogev

Roman Gindin

Ariel Landau

Tsafrir Kamelo

Yoni Labenski

Moti Altahan

Yoram Harel

A controller includes an interface and a processor. The interface is configured to communicate with a nonvolatile memory including multiple memory cells organized in multiple memory blocks that each includes multiple Word Lines (WLs). The processor is configured to store first data in one or more WLs of a memory block, the first data occupies less than a maximal number of WLs available in the memory block, to calculate redundancy data over the first data and store the redundancy data in a dedicated memory, to program second data to a selected WL of the memory block that was not programmed with the first data, to check a programming status resulting from the programming of the selected WL, and in response to identifying that programming the second data to the selected WL has corrupted at least part of the first data, to recover the first data using the redundancy data.

Recovering from failure in programming a nonvolatile memory

A storage device includes storage circuitry and multiple memory blocks. The multiple memory blocks are arranged in an array, and each of the memory blocks includes multiple memory cells. A maximal number of programming cycles that a memory block of the multiple memory blocks sustains depends on a distance of the memory block from an edge of the array. The storage circuitry is configured to apply to the memory blocks programming cycles so that a number of programming cycles that can be applied to a respective memory block is based on a respective distance of the respective memory block from the edge of the array.

Memory block usage based on block location relative to array edge

A memory system includes an interface and storage circuitry. The interface is configured to communicate with a plurality of memory cells that store data by setting the memory cells to analog voltages representative of respective storage values. The storage circuitry is configured to receive data for storage, to measure a temperature at a time of programming the received data, and, to program the received data to the memory cells using a first programming scheme when the measured temperature falls within a predefined normal temperature range, and otherwise to program the received data to the memory cells using a second programming scheme having a lower net storage utilization than the first programming scheme.

Programming schemes for avoidance or recovery from cross-temperature read failures

A controller includes an interface and a processor. The interface is configured to communicate with multiple memory devices over a link. The processor is configured to select at least first and second memory devices for writing, and to write at least first and second data units in sequence to the first memory device over the link, while avoiding writing to any of the other memory devices until transferal of the at least first and second data units over the link has been completed, to write at least one data unit to the second memory device after transferring the at least first and second data units to the first memory device, and, in response to verifying that the first memory device is ready to receive subsequent data, to write to the first memory device at least a third data unit.

Parallel scheduling of write commands to multiple memory devices

A method includes storing data in memory cells by programming the memory cells with respective values. The memory cells are read in multiple readout operations that each compares the programmed values to at least first and second read thresholds, while keeping the first read threshold fixed throughout the readout operations and perturbing only the second read threshold between the readout operations. A preferred value for the second read threshold is estimated based on the multiple readout operations.

Adaptation of high-order read thresholds

A method includes storing data encoded with an ECC in a group of memory cells by writing respective storage values to the memory cells. Multiple sets of readout results are read from the memory cells by comparing the storage values to one or more threshold combinations, each including multiple read thresholds. A plurality of partial syndromes of the ECC is computed, each partial syndrome computed over the readout results that were read using a respective threshold combination. A respective syndrome is calculated for each threshold combination, in at least a subset of all possible threshold combinations, based on one or more of the partial syndromes associated with that threshold combination. A preferred threshold combination is selected, from among the threshold combinations, for which a weight of the respective syndrome is minimal, by processing less than all the partial syndromes associated with all the possible threshold combinations.

Efficient search for optimal read thresholds in flash memory

A device includes a memory and a read/write (R/W) unit. The memory includes multiple gates coupled to a common charge-trap layer. The R/W unit is configured to program and read the memory by creating and reading a set of electrically-charged regions in the common charge-trap layer, wherein at least a given region in the set is not uniquely associated with any single one of the gates.

Storage in charge-trap memory structures using additional electrically-charged regions

A method includes defining a normal voltage configuration for application to word lines (WLs) and Bit lines (BLs) of a memory block, and a an abnormal voltage configuration, different from the normal voltage configuration, for application to the WLs and the BLs of the memory block when a word-line-to-word-line (WL-WL) short-circuit is found between at least two of the WLs in the memory block. If no WL-WL short-circuit is found in the memory block, a data storage operation is performed in the memory block by applying the normal voltage configuration. If a WL-WL short-circuit is found in the memory block, the data storage operation is performed in the memory block by applying the abnormal voltage configuration.

Data storage in a memory block following WL-WL short

A method includes dividing a group of analog memory cells into multiple subsets. The memory cells in the group are sensed simultaneously by performing a single sense operation, while applying to the subsets of the memory cells respective different sets of read thresholds, so as to produce respective readout results. An optimal set of the read thresholds is estimated by processing the multiple readout results obtained from the respective subsets using the different sets of the read thresholds.

Read threshold estimation in analog memory cells using simultaneous multi-voltage sense

An apparatus includes a memory and a memory controller. The memory includes a memory block that includes memory cells connected by word lines. The memory controller is configured to store data in the memory cells, and to identify a suspected short-circuit event in the memory block by recognizing a deviation of a performance characteristic of at least a given word line in the memory block relative to the performance characteristic of remaining word lines in the memory block.

Identifying word-line-to-substrate and word-line-to-word-line short-circuit events in a memory block

A method, in a memory including multiple analog memory cells, includes segmenting a group of the memory cells into a common section and at least first and second dedicated sections. Each dedicated section corresponds to a read threshold that is used for reading a data page to be stored in the group. Data to be stored in the group is jointly balanced over a union of the common section and the first dedicated section, and over the union of the common section and the second dedicated section, to create a balanced page such that for each respective read threshold an equal number of memory cells will be programmed to assume programming levels that are separated by the read threshold. The balanced page is stored to the common and dedicated sections, and the read thresholds are adjusted based on detecting imbalance between data values in readout results of the balanced page.

Threshold adjustment using data value balancing in analog memory device

A method includes calculating redundancy information over a set of data items, and sending the data items for storage in a memory. The redundancy information is retained only until the data items are written successfully in the memory, and then discarded. The data items are recovered using the redundancy information upon a failure in writing the data items to the memory.

Data protection from write failures in nonvolatile memory

A method includes, in a memory that includes two or more memory units, storing a code word of an Error Correction Code (ECC) that is representable by a plurality of check equations, such that a first part of the code word is stored in a first memory unit and a second part of the code word is stored in a second memory unit. A subset of the check equations, which operate only on code word bits belonging to the first part stored in the first memory unit, is identified. The first part of the code word is retrieved from the first memory unit, and a count of the check equations in the identified subset that are not satisfied by the retrieved first part of the code word is evaluated. One or more readout parameters, for readout from the first memory unit, are set depending on the evaluated count.

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Givatayim, Israel

Barak Baum