Broadcom Corporation

Baobinh Truong

Kimming So

Mark Chambers

Gerald Grand

Jason Leonard

Yook-Khai Cheok

Chia-Cheng Choung

A system and method for seamlessly reprogramming clock frequencies includes a phase locked loop (PLL) that generates CPU and double data rate (DDR) clocks. A crystal is used to generate a reference clock. The CPU clock and the reference clock are inputs to a first multiplexer, and the DDR clock and reference clock are inputs to a second multiplexer. In normal operation the multiplexers provide the CPU and DDR clock signal as outputs. To reprogram the clock frequencies and reset the PLL, (1) the reference clock signal is selected to be the output of both multiplexers, so the device is running on the internal reference clock. The mux switching is synchronized with the CPU and DDR clock signals. (2) The PLL is reprogrammed, its internal voltage-controlled oscillator is reset, and the PLL is restarted at the new desired frequency. (3) When the new PLL frequency output is stable, the multiplexers are switched back to the PLL-generated CPU and DDR clocks, synchronously with the reference clock signal.

System and method for maintaining device operation during clock signal adjustments

A system and method for interrupt distribution in a multithread processor are disclosed. A connection between an interrupt and a set of thread processors can be programmed. When the interrupt is executed, the set of thread processors are affected. While executing the thread processor tasks, the connection may be reprogrammed to interrupt another set of thread processors.

System and method for interrupt distribution in a multithread processor

One or more methods and systems of improving the performance of consecutive data stores into a cache memory are presented. In one embodiment, the method comprises writing data into a data array associated with at least a first store instruction while accessing a tag in a tag array associated with at least a second store instruction. In one embodiment, the method of processing consecutive data stores into a cache memory comprises updating a first data in a cache memory while concurrently looking up or identifying a second data in the cache memory. In one embodiment, a system for improving the execution of data store instructions of a CPU comprises a pipelined buffer using a minimal number of data entries, a data array used for updating data associated with a first store instruction, and a tag array used for looking up data associated with a second store instruction.

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San Jose, CA, United States of America

Baobinh Truong