Shanghai Integrated Circuit Manufacturing Innovation Center Co., Ltd.

Fudan University

Shanghai Integrated Circuit Manuvacturing Innovation Center Co., Ltd

Bao Zhu

Wei Zhang

Qingqing Sun

Rui Yin

The present invention provides a metal interconnection structure and a manufacturing method thereof, the metal interconnection structure includes: metal interconnection lines disposed at intervals, first metal layers respectively disposed on the metal interconnection lines; second metal layers respectively disposed on the first metal layers; dielectric layers disposed on both sides of the first metal layer and the second metal layer and having a gap with both the first metal layer and the second metal layer; and a metal diffusion covering layer covering the dielectric layer and the second metal layer. In the present invention, by disposing the dielectric layer on both sides of the first metal layer and the second metal layer, and the dielectric layer has a gap with both the first metal layer and the second metal layer, and the formed metal interconnection structure reduces parasitic capacitance due to the gap, and the gaps existing between the first metal layer and the dielectric layer and between the second metal layer and the dielectric layer can further reduce the diffusion of metal ions to the dielectric layer.

Metal interconnection structure and manufacturing method thereof

The present disclosure discloses a three-dimensional integration system of an RFID chip and a supercapacitor and a manufacturing method thereof. The three-dimensional integration system of an RFID chip and a supercapacitor includes: a silicon substrate (); an RFID chip () disposed on a front surface of the silicon substrate (); a supercapacitor disposed on a back surface of the silicon substrate () at a position corresponding to the RFID chip (), but not in contact with the RFID chip (); through silicon via structures penetrating the silicon substrate () and respectively disposed on two sides of the RFID chip (); wherein the RFID chip () has a chip positive electrode () and a chip negative electrode () electrically connected with a capacitor contact positive electrode () and a capacitor contact negative electrode () of the supercapacitor through the through silicon via structures on the two sides respectively; and a packaging substrate () electrically connected to the capacitor contact positive electrode () and the capacitor contact negative electrode ().

Three-dimensional integrated system of RFID chip and super capacitor and preparation method thereof

The present disclosure belongs to the technical field of integrated circuit packaging, and specifically relates to a through silicon via structure for three-dimensional integrated circuit packaging and a manufacturing method thereof. The method of the present disclosure includes the following steps: lifting off a silicon wafer by implanting hydrogen ions into the silicon wafer to obtain a substrate for making a through silicon via; performing double-sided plasma etching on the substrate to form a through silicon via penetrating the substrate; depositing an insulating medium, a copper diffusion barrier layer, and a seed layer; and removing parts of the copper diffusion barrier layer and the seed layer by photolithography and etching processes, leaving only parts of the copper diffusion barrier layer and the seed layer on a sidewall of the through silicon via; forming a sacrificial layer on the upper and lower surfaces of the resulting structure, completely filling in the through silicon via with conductive metal material, and then removing the sacrificial layer, upper and lower surfaces of the conductive metal material respectively protruding from upper and lower surfaces of the insulating medium; and forming a contact pad on a surface of the conductive metal material. The present disclosure can effectively improve production efficiency and lower the cost.

Through silicon via structure for three-dimensional integrated circuit packaging and manufacturing method thereof

Disclosed is an SOI active interposer for three-dimensional packaging and a fabrication method thereof. An SOI substrate is used as the substrate, and a CMOS inverter is formed on the top silicon of the SOI by using standard integrated circuit manufacturing processes, so that short channel effect and latch-up effect can be suppressed. A via hole structure is etched on the SOI substrate between the PMOS and NMOS transistors of the CMOS inverter, which on the one hand can be used as a conductive channel between the chips in a vertical direction, and on the other hand, can be used as an electrical isolation layer between the PMOS and NMOS transistors.

SOI active transfer board for three-dimensional packaging and preparation method thereof

Disclosed is a three-dimensional integrated system for DRAM chips and a fabrication method thereof. A plurality of trench structures are etched on the front and back of a silicon wafer; then, a TSV structure is etched between the two upper and lower trenches opposite to each other for electrical connection; then, DRAM chips are placed in the trenches, and copper-copper bonding is used to make the chips electrically connected to the TSV structure in a vertical direction; finally, redistribution is done to make the chips in a horizontal direction electrically connected. The invention can make full use of silicon materials, and can avoid problems such as warpage and deformation of an interposer. In addition, placing the chips in the trenches will not increase the overall package thickness, while protecting the chips from external impact.

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Shanghai, China

Bao Zhu