Taiwan Semiconductor Manufacturing Comp. Ltd.

Taiwan Semiconducotr Manufacturing Company, Ltd.

Bao-Ru Young

Tung-Heng Hsieh

Harry-Hak-Lay Chuang

Ming Zhu

Lee-Wee Teo

Wei Cheng Wu

Jin-Aun Ng

Po-Nien Chen

Yung Feng Chang

Hui-Wen Lin

Harry Hak-Lay Chuang

Sheng-Chen Chung

Hak-Lay Chuang

Tzung-Chi Lee

Chia-Sheng Fan

Chun-Chia Hsu

Yu-Ying Hsu

Kong-Beng Thei

Chiung-Han Yeh

Yi-Jyun Huang

Chun-Yen Lin

Hsien-Huang Liao

Ryan Chia-Jen Chen

Huan-Just Lin

Chih-Yang Yeh

Chia Ming Liang

Maxi Chang

Sheng-Hsiung Wang

Yu-Jung Chang

Pang-Chi Wu

Meng-Fang Hsu

Kong-Pin Chang

Sin-Hua Wu

Chia-Shiung Tsai

Kuo-Cheng Ching

Chao-Cheng Chen

Pei-Ren Jeng

Chih-Tang Peng

Kuo-Yi Chao

Yuan-Sheng Huang

Jen-Sheng Yang

Yuan-Tien Tu

Ta-Wei Lin

Jung-Hui Kao

Shih-Hao Lo

Shih-Chieh Wu

Ting-Hua Hsieh

Yung-Feng Chang

Carlos H Diaz

Mei-Yun Wang

Cheng-Cheng Kuo

Yen-Sen Wang

Jyun-Ming Lin

Ching-Che Tsai

Chung-Hau Fei

Jam-Wem Lee

Kuo-Ji Chen

Ming-Hsiang Song

Ching-Feng Fu

Shih-Ting Hung

Chih-Hung Wang

Chi-Hsun Hsieh

Eric Huang

Tun-Jen Chang

Ming-Yang Huang

Ming-Ching Chang

Harry Chuang

Yu Chao Lin

Tsung-Chieh Tsai

Chien-Liang Chen

Yuh-Jier Mii

Yen-Chun Lin

Yi-Ren Chen

Jhe-Ching Lu

Tsai-Chun Li

Chi-Ju Lee

Tze-Liang Lee

Wei-Cheng Wu

Chii-Horng Li

Chun-Hung Chen

Yen-Ru Lee

Wen-Chuan Chiang

Kuei Shun Chen

Chung-Yi Lin

George Liu

Li-Chih Chao

Shao-Jyun Wu

Shwangming Jeng

Wang-Jung Hsueh

Han-Guan Chew

Wen-Chih Yang

Carlos Hernando Diaz

Ting-Yun Wu

Kai-Shyang You

Cheng Cheng Kuo

Der-Fang Huang

Tsung-chieh Tsai

Kun-I Lee

Yuhi-Jier Mii

A method for forming a pattern layout is provided, including receiving an IC design layout including a layout block, a first line pattern is disposed inside the layout block along the first direction; forming a second line pattern disposed outside the layout block parallel to the first line patterns; forming a mandrel bar pattern oriented along the second direction and overlapping the first line pattern and the second line pattern, the mandrel bar pattern is between the first edge and the third edge of the layout block that are parallel to the first direction, and a first end of the mandrel bar pattern is separated from the first edge and overlaps a first side edge of one of the first line pattern or the second line pattern closest to the first edge; and outputting a pattern layout.

Methods for forming pattern layout, mask, and semiconductor structure

The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Polysilicon design for replacement gate technology

In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.

Semiconductor devices

A fuse structure includes first and second transistors where each of the first and the second transistors has a source terminal, a drain terminal, and a gate terminal; a first source/drain contact disposed on the source terminal of the first transistor; a second source/drain contact disposed on the drain terminal of the second transistor; an insulator disposed laterally between the first and the second source/drain contacts; a source/drain contact via disposed on the first source/drain contact; and a program line connected to the source/drain contact via, wherein a width of the insulator is configured such that a programming potential applied across the source/drain contact via and the drain terminal of the second transistor causes the insulator to break down.

Fuse structure

A method for making an integrated circuit (IC) includes inserting black boxes into a layout of the IC; connecting the black boxes with a connectivity network; and inserting first dummy patterns in areas of the layout outside of the black boxes and the connectivity network. After the inserting of the first dummy patterns, the method further includes replacing the black boxes with circuit macros that have one-to-one correspondence with the black boxes, wherein each of the circuit macros includes circuit patterns in a central area of the respective circuit macro and second dummy patterns surrounding the central area. In the method, at least one of the following operations is performed by an electronic design automation (EDA) tool: the inserting of the black boxes, the connecting of the black boxes, the inserting of the first dummy patterns, and the replacing of the black boxes with the circuit macros.

Method for chip integration

A semiconductor device structure and a formation method are provided. The method includes forming a first fin structure, a second fin structure, a third fin structure, and a fourth fin structure over a substrate. The second fin structure is between the first fin structure and the third fin structure, and the third fin structure is between the second fin structure and the fourth fin structure. A first lateral distance between the first and the second fin structures is greater than a second lateral distance between the third and the fourth fin structures. The method also includes forming a first p-type epitaxial structure over the first fin structure and forming a second p-type epitaxial structure over the second fin structure. The method further includes forming a first n-type epitaxial structure over the third fin structure and forming a second n-type epitaxial structure over the fourth fin structure.

Structure and formation method of semiconductor device with epitaxial structures

A method for forming a semiconductor device structure includes forming a fin structure with alternating stacked first semiconductor layers and second semiconductor layers over a substrate. The method also includes forming a cladding layer over the fin structure. The method also includes forming a fin isolation structure beside the cladding layer. The method also includes forming a capping layer over the fin isolation structure. The method also includes forming a dummy gate structure across the capping layer. The method also includes patterning the dummy gate structure. The method also includes patterning the capping layer by using the dummy gate structure as a mask layer. The method also includes removing the dummy gate structure.

Semiconductor device structure and method for forming the semiconductor device structure

A semiconductor device and method includes: forming a first fin and a second fin on a substrate; forming a dummy gate material over the first fin and the second fin; forming a recess in the dummy gate material between the first fin and the second fin; forming a sacrificial oxide on sidewalls of the dummy gate material in the recess; filling an insulation material between the sacrificial oxide on the sidewalls of the dummy gate material in the recess; removing the dummy gate material and the sacrificial oxide; and forming a first replacement gate over the first fin and a second replacement gate over the second fin.

Semiconductor devices having fins and multiple isolation regions

An IC includes a first standard cell (SC) having a first circuit area (CA) and a first transition area (TA) placed on an edge of the CA; and a SChaving a CAand a TAplaced on an edge of CA'. CAincludes a first and a second active region (ARand AR) longitudinally oriented along a first direction (D), and a first gate stack (G) along a D⊥Dand extending over ARand AR. Gincludes a first gate segment (GS) contacting ARand a GScontacting AR. GSand GSare different in composition. GSand GSare associated with a pFET and a nFET, respectively. TAincludes a Glongitudinally oriented along Dand spans between opposite cell edges of the SC. Gis a lengthwise uniform gate stack. SCis placed in abutment with the SCsuch that TAand TAshare a common edge.

Integrated standard cell structure

A semiconductor structure includes a substrate having a first well of a first conductivity type and a second well of a second conductivity type. From a top view, the first well includes first and seconds edges extending along a first direction. The second edge has multiple turns, resulting in the first well having a protruding section and a recessed section. The semiconductor structure further includes a first source/drain feature over the protruding section and a second source/drain feature over a main body of the first well. The first source/drain feature is of the first conductivity type. The second source/drain feature is of the second conductivity type. The first and the second source/drain features are generally aligned along a second direction perpendicular to the first direction from the top view.

Semiconductor structures having wells with protruding sections for pickup cells

A method includes forming a fin structure over a substrate, forming a first source/drain feature and a second source/drain feature over the fin structure, forming a dielectric material over the first source/drain feature and the second source/drain feature, patterning the dielectric layer into insulating features, and forming a first contact plug on the first source/drain feature and a second contact plug on the second source/drain feature. The insulating features include a first insulating feature and a second insulating feature on opposite sides of the first source/drain feature, and a third insulating feature and a fourth insulating feature on opposite sides of the second source/drain feature. The first insulating feature is longer than the third insulating feature. The distance between the first and second insulating features is greater than the distance between the third and fourth insulating features.

Semiconductor structure and method for forming the same

Electrostatic discharge (ESD) structures are provided. An ESD structure includes a semiconductor substrate, a first epitaxy region with a first type of conductivity over the semiconductor substrate, a second epitaxy region with a second type of conductivity over the semiconductor substrate, and a plurality of semiconductor layers. The semiconductor layers are stacked over the semiconductor substrate and between the first and second epitaxy regions. A first conductive feature is formed over the first epitaxy region and outside an oxide diffusion region. A second conductive feature is formed over the second epitaxy region and outside the oxide diffusion region. A third conductive feature is formed over the first epitaxy region and within the oxide diffusion region. A fourth conductive feature is formed over the second epitaxy region and within the oxide diffusion region. The oxide diffusion region is disposed between the first and second conductive features.

ESD structure

An array of poly lines on an active device area of an integrated chip is extended to form a dummy device structure on an adjacent isolation region. The resulting dummy device structure is an array of poly lines having the same line width, line spacing, and pitch as the array of poly lines on the active device area. The poly lines of the dummy device structure are on grid with the poly lines on the active device area. Because the dummy device structure is formed of poly lines that are on grid with the poly lines on the active device area, the dummy device structure may be much closer to the active device area than would otherwise be possible. The resulting proximity of the dummy device structure to the active device area improves anti-dishing performance and reduces empty space on the integrated chip.

Dummy poly layout for high density devices

A device includes a semiconductor substrate, an active region over the semiconductor substrate extending lengthwise in a first direction, a gate structure over the active region extending lengthwise in a second direction perpendicular to the first direction, a source feature and a drain feature on the active region and interposed by the gate structure, a source contact on the source feature, a drain contact on the drain feature, and a via rail over the substrate spaced from the active region. The via rail includes a main portion extending lengthwise in the first direction having a sidewall surface facing opposite the end surface of the drain contact, and a jog via extending from the main portion along the second direction and having a sidewall surface facing the second direction, each of the main portion and the jog via contacting the source contact.

Via rail structure

In some embodiments, the present disclosure relates to a method that includes removing portions of a substrate to form a continuous fin protruding from an upper surface of the substrate. A doping process is performed to selectively increase a dopant concentration of a first portion of the continuous fin. A first gate electrode is formed over a second portion of the continuous fin, and a second gate electrode is formed over a third portion of the continuous fin. The first portion of the continuous fin is between the second and third portions of the continuous fin. A dummy gate electrode is formed over the first portion of the continuous fin. Upper portions of the continuous fin that are arranged between the first gate electrode, the second gate electrode, and the dummy gate electrode are removed, and source/drain regions are formed between the first, the second, and the dummy gate electrodes.

Leakage reduction between two transistor devices on a same continuous fin

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Zhubei, Taiwan

Bao-Ru Young