Topside Research, LLC

General Instrument Corporation

General Instrument Corporation of Delaware

Motorola Corporation

Bao K Vuong

Heath Stewart

Chris Haywood

Nadim Shaikli

Chris Hoogenboom

Thomas C Reiner

Ken Wong

Adam Rappoport

Michael J De La Garrigue

Candace M Anderson

Yaxin Shui

Phil Terry

Kevin Robertson

Quang Hong

Mike De La Garrigue

There is disclosed an interface device for interfacing between a main processor and one or more processing engines. The interface device is configurable, so that it may be used with a wide range of processing engines without being redesigned.

Interface device for interfacing a main processor to processing engines and classifier engines, and methods for configuring and operating interface devices

There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.

Optimized switching method

Switch for bus optimization

A method and apparatus for downsizing a digital video image, such as an image corresponding to the MPEG-2 standard. The system is particularly suitable for providing a reduced image for a picture-in-picture mode on a television. Digital video pixel data that is received from a channel is decompressed to provide pixel data of an original image (e.g., A A A A ). Horizontally adjacent pixel pairs of the original image are averaged to provide horizontally downsized pixel data (e.g., (A &plus;A )/2, (A &plus;A )/2), which is stored in a first bank of a multi-bank memory. Data from every other pixel of the original image (e.g., A A ) is stored in a second bank of the dual-bank memory. To obtain a downsized image, vertically adjacent lines of the horizontally downsized pixel data are retrieved from the first bank, and averaged to provide vertically and horizontally downsized pixel data for display. Alternatively, to recover pixel data corresponding to the original image for decompressing predictive-coded images, portions of the horizontally downsized pixel data may be retrieved from the first bank with corresponding portions of the data from the second bank (e.g., A &equals;2(A &plus;A )/2&minus;A ).

Synchronous DRAM bandwidth optimization for display downsizing of an MPEG-2 image

A method and apparatus for converting a digital video image to a higher aspect ratio format at a decoder by line dropping. For example, conversion from a 4:3 to a 16:9 letterbox format may be achieved. Line dropping for non-anchor pictures (e.g., B-pictures) occurs on a decoding-side of the decoder, prior to storage in memory. Line dropping for anchor pictures (e.g., I- and P-pictures) occurs on a display-side of the decoder, after being retrieved from the memory, and prior to display. Additional memory space is freed to allow storage of additional decoded data, thus compensating for the decrease in display processing time caused by a reduced number of active video lines that are processed with the letter box format.

16:9 aspect ratio conversion by letterbox method for an MPEG image

Pixel data is stored and subsequently read from a random access memory of a video decompression processor in a manner that reduces the number of times different rows of the RAM must be addressed in order to retrieve portions of the pixel data therefrom. Pixel data from a video frame is stored in the RAM as a plurality of pages. Each page substantially fills a different row of the RAM and corresponds to a different section of the video frame. A motion vector is decoded to determine the location of a prediction area within the video frame. In the event that the prediction area encompasses more than one of the pages of the video frame, the pixel data is retrieved one page at a time, minimizing the number of row changes required when addressing the RAM to retrieve the data.

Method and apparatus for efficient addressing of DRAM in a video

A method and apparatus are disclosed for interpolating pixels to obtain subpels for use by a video decompression processor. A prediction area is defined from which subpels are necessary to decompress a portion of a video image. Instead of reading all of the pixels from the prediction area and then processing them together to perform the necessary interpolation, portions of the pixel data are read and simultaneously averaged using in-place computation in order to reduce hardware requirements. Rounding of subpixel results is achieved using the carry input of conventional adders to add a binary '1' to the averaged pixels, which are subsequently truncated to provide the interpolated subpels.

Pixel interpolation filters for video decompression processor

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San Diego, CA, United States of America

Bao K Vuong