International Business Machines Corporation

Bao G Truong

Anand Haridass

Roger Donell Weekly

Andreas Huber

Joel David Ziegelbein

Daniel Mark Dreps

Michael J Lee

Samuel I Ward

Daniel Douriet

Colm Brian O'Reilly

Michael Ju Hyeok Lee

John Cummings Schiff

Emiliano Lozano

Wiren Dale Becker

Glen Arthur Wiedemeier

Vinod Ramadurai

Ricardo H Nigaglioni

William David Ramsour

Carlos I Gomez

David Nolan Ault

Patrick R Crosby

Gahn Wattanadilok Krishnakalin

Eddie K Chan

A memory includes an array of memory cells that form rows and columns. The rows of the array include memory cell pairs. The memory cells may include two cross-coupled inverters and two pass-devices that couple to alternate sides of the cross-coupled inverters. The two memory cells of a memory cell pair share a common intra-pair bitline. Adjacent memory cell pairs share a common inter-pair bitline. To perform a data read operation on a particular memory cell in a memory cell pair in the rows and columns of the array, wordline drive circuitry transmits wordline activate signals to select both the row for the data read operation and a particular one of the pair of memory cells for the data read operation.

Volatile memory access via shared bitlines

A mechanism is provided for enabling a proper write through during a write-through operation. Responsive to determining the memory access as a write-through operation, first circuitry determines whether a data input signal is in a first state or a second state. Responsive to the data input signal being in the second state, the first circuitry outputs a global write line signal in the first state. Responsive to the global write line signal being in the first state, second circuitry outputs a column select signal in the second state. Responsive to the column select signal being in the second state, third circuitry keeps a downstream read path of the cache access memory at the first state such that data output by the cache memory array is in the first state.

Preventing fast read before write in static random access memory arrays

Performing a calculation using a coordinate rotation digital computer (CORDIC) algorithm. Execution of the CORDIC algorithm is begun. An error introduced by a truncated vector as a result of executing the CORDIC algorithm is pre-computed. The error is incorporated into a subsequent iteration of the CORDIC algorithm. Execution of the CORDIC algorithm is completed. The result of the CORDIC algorithm is stored.

Accuracy improvement in CORDIC through precomputation of the error bias

A mechanism is provided for gating a read access of any row in a cache access memory that has been invalidated. An address decoder in the cache access memory sends a memory access to a non-gated wordline driver and a gated wordline driver associated with the memory access. The non-gated wordline driver outputs the data stored in a valid bit memory cell to the gated wordline driver in response to the non-gated wordline driver determining the memory access as a read access. The gated wordline driver determines whether the data from the valid bit memory cell from the non-gated wordline driver indicates either valid data or invalid data in response to the gated wordline driver determining the memory access as a read access and denies an output of the data in a row of memory cells associated with the gated wordline driver in response to the data being invalid.

Cache array power savings through a design structure for valid bit detection

A method comprises generating a test pattern for a device under test (DUT), wherein the DUT comprises a plurality of scan chains coupled to a plurality of multiple input shift registers (MISRs). The plurality of faults detected by a first MISR and by a second MISR are identified. In the event the plurality of faults detected by the first MISR does not include any of the plurality of faults detected by the second MISR and the plurality of faults detected by the second MISR does not include any of the plurality of faults detected by the first MISR, the first MISR and the second MISR are coupled as an independent MISR pair. The test pattern is applied to the DUT to generate a scan chain output. The independent MISR pair captures the scan chain output to generate a test signature. The test signature is compared with a known good signature.

Scan chain fail diagnostics

A circuit for detecting noise events in a system with time variable operating points is provided. A first voltage, which is averaged over time, is compared to a second voltage. A signal is generated to instruct circuits within a processor to initiate actions to keep a voltage from drooping further.

Method for detecting noise events in systems with time variable operating points

A mechanism for reducing the vertical cross-talk interference experienced in signal lines due to the inductive affects from signal lines in other signal planes of a multi-layer ceramic package is provided. With the apparatus and method, one or more vias in the multi-layer ceramic package may be removed from the structure to provide area through which an offset of the signal lines may pass. Because these offsets of the signal lines exist in parallel planes above or below each other, with no ground lines existing directly between these signal line offsets, a capacitive cross-talk is introduced into the signal lines. This capacitive cross-talk is opposite in polarity to the inductive cross-talk already experienced by the signal lines. As a result, the capacitive cross-talk tends to negate or reduce the inductive cross-talk thereby reducing the far end noise in the signal line.

Ceramic package in which far end noise is reduced using capacitive cancellation by offset wiring

A driver circuit is configured as a frequency compensated differential amplifier having one input coupled to a first data signal and a second input coupled to a second data signal. Each stage of the differential amplifier is biased with a current source. The driver circuit generates a first output signal coupled to the input of a first transmission line and a second output signal coupled to the input of a second transmission line. The first and second output signals are generated as the difference between the first and second data signals amplified by a compensated gain. A compensation network that attenuates the low frequency components of the input signals relative to the high frequency components is coupled between current sources biasing the differential amplifier. The outputs of the first and second transmission lines are coupled to the inputs of a differential receiver that may or may not be frequency compensated.

Differential transmitter circuit

An information handling system (IHS) includes a processor with on-chip or off-chip SRAM array. After a read operation, a control circuit may instruct the SRAM array to conduct a precharge operation, or alternatively, instruct the SRAM array to conduct an equalize bitline voltage operation. A read operation may follow the precharge operation or the equalize bitline voltage operation. The control circuit may instruct the SRAM array to conduct an equalize bitline voltage operation if an equalized voltage of a bitline pair exhibits more that a predetermined amount of voltage. Otherwise, the control circuit instructs the SRAM array to conduct a precharge operation before the next read operation.

Information handling system with SRAM precharge power conservation

Mechanisms for multiple hit (multi-hit) detection in associative memories, such as a content addressable memory (CAM), are provided. The illustrative embodiments include a hit bitline that discharges as RAM side entries of the associative memory are accessed. The hit bitline is precharged high and pulled low by a series of devices that are activated as each RAM side row is accessed. As more RAM side rows are accessed, the hit bitline drops lower in voltage. The hit bitline drives an inverter with a threshold set such that any voltage equal to or lower than the threshold indicates a multi-hit situation. Any voltage higher than the threshold indicates a single hit or 'no-hit' situation. Thus, from the voltage of the hit bitline, the presence of a multi-hit condition may be detected.

Multi-hit detection in associative memories

A mechanism is provided for transparent multi-hit correction in associative memories. A content associative memory (CAM) device is provided that transparently and independently executes a precise corrective action in the case of a multiple hit being detected. The wordlines of a CAM array are modified to include a valid bit storage circuit element that indicates whether or not the corresponding wordline is valid or not. In operation, if multiple hits are detected, the multiple hit is signaled to the host system and the particular entries in the CAM array corresponding to the multiple hits are invalidated by setting their associated valid bit storage circuit elements to an invalid value or clearing the value in the associated valid bit storage circuit element. Any data returned to the host system as a result of the multiple hits is invalidated in the host system in response to the signaling of the multiple hits.

Transparent multi-hit correction in associative memories

A method is provided that uses non-linear data compression in order to generate a set of test vectors for use in scan testing an integrated circuit. The method includes the steps of initially designing the set of test vectors, and selecting one of multiple available coding schemes for each test vector wherein at least two of the coding schemes selected for encoding are different from one another, and wherein one of the available coding schemes represents non-encoded data. The method further comprises operating a random pattern generator to generate data blocks, each corresponding to one of the test vectors, wherein the data block corresponding to a given test vector is encoded with a bit pattern representing the coding scheme of the given test vector. The corresponding data block also has a bit length that is less than the bit length of the given test vector. Each data block is routed to a plurality of decoders, wherein each decoder is adapted to recognize only one of the coding schemes represented by one of the bit patterns. The decoder recognizing the coding scheme of the data block decodes the bit pattern of the data block and generates the test vectors corresponding to the data block.

Method using non-linear compression to generate a set of test vectors for use in scan testing an integrated circuit

A system for mitigating power supply and power distribution system noise response by throttling execution units based upon voltage sensing in a circuit is provided. A sensing unit senses the voltage of a circuit. The sensing unit determines if the execution of another execution unit will cause the circuit voltage to drop below a threshold level. In response to a determination that the execution of another execution unit will cause the circuit voltage to drop below the threshold level, the execution unit is throttled.

Mitigate power supply noise response by throttling execution units based upon voltage sensing

A first clock signal of frequency F is used to couple data to an off-chip driver (OCD) using a master/slave flip flop (FF), wherein the master latch is clocked with the first clock signal and the slave latch is clocked with the complement of the first clock signal. A second clock signal of frequency F/is generated from the first clock signal. The second clock signal is shifted a time equal to substantially one-half the cycle of the first clock signal. In one embodiment, the second clock is shifted using a delay line circuit. In another embodiment, the second clock is shifted using a master/slave FF, wherein the master latch is clocked with the complement of the first clock signal and the slave latch is clocked with the first clock signal. The logic state transitions of the data between edges of the propagating clock thereby reducing coupling to the clock transitions and thus reducing edge jitter.

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Austin, TX, United States of America

Bao G Truong