Black Sesame Technologies Inc.

Bangjian Ouyang

Wei Qin

Zhitao Wang

An improved system for monitoring clock duty cycles, comprising: a first monitoring circuit configured to record a first quantity of high levels of the monitored clock signal sampled by a first random clock signal; a second monitoring circuit configured to record a second quantity of high levels of the monitored clock signal sampled by a second random clock signal, wherein the phase of the second random clock is adjusted by a second adjustment degree based on a first clock; a third monitoring circuit configured to record a third quantity of high levels of the monitored clock signal sampled by a third random clock signal, wherein the phase of the third random clock is the reverse of that of the first random clock; and a calculation module configured to determine a duty cycle of the monitored clock based on the first quantity, the second quantity, and the third quantity.

Method and system for monitoring clock duty cycles

The disclosure provides a bus-based communication system, which comprises a bus controller, a first buffer, a bus redundant controller, a second buffer and a comparator. The bus controller is configured to receive a bus input signal and send a bus output signal. The first buffer is connected with the bus controller in parallel to receive the bus input signal, and is configured to output the bus input signal after a preset time, wherein the preset time is two or more duty cycles of the bus controller. The bus redundant controller is connected to an output terminal of the first buffer and configured to receive a bus output signal delayed by at least T cycles output by the first buffer and output a bus redundant output signal.

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Shenzhen, China

Bangjian Ouyang