Taiwan Semiconductor Manufacturing Comp. Ltd.

Bang-Yu Huang

Chui-Ya Peng

Chih-Fen Chen

Yeh-Hsun Fang

Tsung-Ying Liu

Ching-Wen Chen

Chun-Hsu Yen

In a method for semiconductor processing, a semiconductor substrate is provided. The semiconductor substrate defines at least one first trench therein. The at least one first trench has a first depth (d). A coating layer is deposited onto the semiconductor substrate using at least one precursor under a setting for a processing temperature (T). The coating layer defines at least one second trench having a second depth (d) above the at least one first trench. A first depth parameter (t) of the second depth (d) relative to the first depth (d) is determined. The processing temperature (T) is then determined based on the first depth parameter (t).

Method for calibrating temperature in chemical vapor deposition

In a method for semiconductor processing, a semiconductor substrate is provided. The semiconductor substrate defines at least one first trench therein. The at least one first trench has a first depth (d). A coating layer is deposited onto the semiconductor substrate using at least one precursor under a setting for a processing temperature (T). The coating layer defines at least one second trench having a second depth (d) above the at least one first trench. A depth parameter (t) the second depth (d) relative to the first depth (d) is determined. The processing temperature (T) is then determined based on a pre-determined standard reference curve comprising a plurality of references depth parameters in a first range as a function of a plurality of reference processing temperatures in a second range.

A method for fabricating a shallow trench isolation includes forming a trench in a substrate, forming a bottom shallow trench isolation dielectric filling a gap of the trench, and forming a top shallow trench isolation dielectric on the bottom shallow trench isolation. The bottom shallow trench isolation dielectric has a concave center portion, and the top shallow trench isolation dielectric is deposited on the bottom shallow trench isolation by a high density plasma chemical vapor deposition process using low deposition to sputter ratio. A semiconductor structure having the shallow trench isolation is also disclosed.

Method for fabricating shallow trench isolation and semiconductor structure using the same

A semiconductor device includes a substrate, a gate stack, at least one epitaxy structure, a dielectric material, and a contact. The gate stack is present on the substrate. The gate spacer is present on a sidewall of the gate stack. The epitaxy structure is partially present in the substrate. The dielectric material is present on the substrate and between the epitaxy structure and the gate spacer. The contact is present on the epitaxy structure, the dielectric material, and the gate spacer.

Growing community of inventors

Zhubei, Taiwan

Bang-Yu Huang