Samsung Electronics Co., Ltd.

Bang-Won Lee

In-Hwan Hwang

Hye-Kyoung Lee

Yi-Sung Bae

Dong-hoi Kim

Kyoung-Un Hwang

A data transmission circuit for a digital signal processor chip having a plurality of function blocks, a plurality of global buses which may be selectively connected to each other, and a plurality of local buses which may be selectively connected to an associated global bus and an associated function block. The circuit includes a plurality of first switches for selectively connecting the plurality of local buses to both the plurality of function blocks and the plurality of global buses, and a plurality of second switches means for selectively connecting the plurality of global buses. In a data transmission method for a digital signal processor chip, only those local buses and global buses necessary for data transmission are connected when data is transmitted between the plurality of function blocks. Therefore, movement of data through buses irrelevant to the desired operation is eliminated, and electrical consumption is reduced.

Data transmission circuit for digital signal processor chip and method

An integrated PCM-CODEC circuit including a plurality of PCM subscriber lines consisting of a SLIC for interfacing a telephone line with a switching system, an impedance conformer and a PCM-CODEC, a common bus for transferring a telephone signal into or from a subscriber according to the time division rule for the timing of telephone line use, a telemetering signal source and a (synchronization signal for controlling portion of the telephone call called by the n'th subscriber. The PCM-CODEC circuit includes a buffer, a signal selector, an applied gain controller, an anti-aliasing filter, a telemetering signal filter, a BPF, a coder, a decoder, a LPF, a received-gain controller, a smoothing filter, an operational amplifier and a telemetering gate.

Integrated PCM-CODEC circuit with telemetering noise elimination

In an operational amplifier or a comparator, a slew rate speed-up circuit improving the slew rate, without added power consumption, is disclosed. In a preferred embodiment, an operational amplifier, having one differential amplifier and a first pull-up transistor 10 having a gate connected to an output terminal 23 of the differential amplifier, includes a first output terminal 25, a second pull-up transistor 9 having a gate connected to the output terminal 23 of the differential amplifier and having a channel connected between a power supply voltage terminal and the first output terminal, a second output terminal 26 connected to one end of the channel of the first pull-up transistor 10, a current regulating means 30, connected between the first output terminal and the second output terminal, having one common current path, one pull-up current path and one pull-down current path, a first pull-down transistor 11 having a channel connected between the second output terminal and a ground voltage terminal, and a second pull-down transistor 8 having a channel connected between the first output terminal and the ground voltage terminal.

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Kwangmyeong, South Korea

Bang-Won Lee