Intersil Americas Inc.

Rockwell Technologies, Inc.

Other

University of California

Bang-Sup Song

Kantilal Bacrania

Mario Sanchez

J Mikko Hakkarainen

Eric C Sung

Hsin-Shu Chen

Brian L Allen

Alex R Bugeja

Circuits that provide a gate boost to address non-linear threshold voltage variation in a CMOS T/H circuit. In embodiments of the invention, a boost capacitor and a feedback amplifier add a signal-dependent threshold voltage to the switch gate over-drive voltage of a switch that controls track and hold circuit sampling. In a modified embodiment, capacitive boost is omitted and the feedback amplifier provides the signal-dependent threshold voltage boost. In another embodiment, a boost capacitor and a diode connected transistor provide the signal-dependent threshold voltage boost. In a modified embodiment, capacitive boost is omitted and the diode connected transistor provides the signal-dependent threshold voltage.

Switch linearized track and hold circuit for switch linearization

A dual pump circuit including a transmission gate and a dual charge pump. The transmission gate includes a p-channel transistor and an n-channel transistor, each having a control terminal and a pair of current terminals coupled between a dual pump input and a dual pump output. The dual charge pump includes first and second pump circuits, where each pump circuit is coupled to the dual pump input and to a control terminal of a corresponding one of the transmission gate transistors. Each pump circuit is operative to linearize operation of its corresponding transmission gate transistor by maintaining VGS&mdash;VT constant. The dual pump circuit is used in a track and hold circuit including at least one dual pump sampling circuit, at least one sampling capacitor, and a control circuit for controlling input signal sampling timing. Each dual pump sampling circuit includes the transmission gate and a dual charge pump.

Track and hold with dual pump circuit

A compensation system for calibrating an amplifier having a compensation input including a sigma delta converter, a counter, a memory, adjust logic, a DAC, a pair of compensation capacitors, and a pair of current to voltage (I/V) converters. The converter converts an offset voltage to a bit stream. The counter stores a sum value indicative of the output offset. The memory stores a digital bias value. The adjust logic determines an adjust value based on the sum value and adjusts the stored digital bias value based on the adjust value. The DAC converts the digital bias value to a differential bias current. The compensation capacitors apply a compensation voltage to a compensation input of the amplifier. The I/V converters charge the compensation capacitors using the differential bias current. The adjust logic may use upper and lower thresholds and adjust the digital bias value by one LSB for each compensation cycle.

System and method of DC calibration of amplifiers

A calibration system and method for a resistor ladder that employs relative measurement and adjustment between pairs of resistors. The system includes a resistor tree of complementary pairs of programmable resistors coupled to the resistor ladder, a measurement circuit that measures voltage differences between complementary pairs of programmable resistors, and control logic. The control logic controls the measurement circuit to measure a voltage difference between each complementary pair of programmable resistors and adjusts the relative resistance of each complementary pair of programmable resistors to equalize voltage. The measurement is facilitated by a sigma-delta ADC that converts a measured voltage difference into a bit stream. The programmable resistors are implemented with binary weighted resistors that are digitally adjusted one LSB at a time. Lower and upper adjustment thresholds may be employed to avoid unnecessary over-adjustments while maintaining a requisite level of accuracy.

Calibration of resistor ladder using difference measurement and parallel resistive correction

A multistage ADC that subranges and interpolates, and that amplifies selected subranges to convert an analog signal to a stream of digital values. The ADC samples the analog signal and provides a stream of sample signals. A first stage flash converts each sample signal into a first multiple bit value and subranges a reference ladder according to the first multiple bit value into selected reference signals. Each additional secondary stage amplifies a selected subrange of signals from a prior stage, flash converts the amplified residual signals to provide an additional multiple bit value, interpolates each set of amplified residual signals and subranges the interpolated signals according to the corresponding multiple bit value. A final stage amplifies and flash converts to determine a final multiple bit value. An error corrector combines each set of multiple bit values into a digital value.

Analog to digital converter using subranging and interpolation

A track and attenuate (T/A) circuit for use with switched current source DACs is connected across the DAC's differential current outputs. The T/A circuit includes three attenuate switches: first and second single-ended switches which connect the positive and negative sides of the differential output, respectively, to signal ground, and a third, differential switch which connects the positive and negative output lines together. The three attenuate switches are closed simultaneously during a portion of each cycle of the DAC's sample clock, to attenuate the DAC's current outputs while the outputs of the switched current sources are settling&mdash;thereby preventing dynamic nonlinearities from being introduced into the differential output current. When properly sized, the three attenuate switches (when closed) reduce the differential output current to near zero and lower the common mode voltage between the positive and negative output lines, significantly improving the DAC's dynamic linearity.

Track/attenuate circuit and method for switched current source DAC

A self-trimming current source for used in a switched current source DAC is made from a fixed current source and a variable current source, which are connected in parallel to provide a total output current. The total output current is automatically calibrated by temporarily switching one side of the self-trimming current source to a measurement circuit. Based on the measured value, the variable current source is adjusted to make the total output current equal to a predetermined value. The fixed current source is implemented with a complementary pair of field-effect transistors (FETs) connected in a cascode connection, with the two drain terminals presenting high impedances to the circuitry to which they are connected. A DAC typically includes a plurality of self-trimming current sources, each of which is calibrated during each DAC conversion cycle.

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La Jolla, CA, United States of America

Bang-Sup Song