Seagate Technology Incorporated

Stmicroelectronics S.a.

Agere Systems Inc.

Codelucida, Inc.

Bane Vasic

Erozan Mehmet Kurtas

David Declercq

Alexander Kuznetsov

Jeffrey Lee Sonntag

Shashi Kiran Chilappagari

Inkyu Lee

Benedict J Reynwar

Shiva Kumar Planjery

Jongseung Park

A method and apparatus for encoding low-density parity check codes uses parity check matrices composed of circulant blocks. The apparatus operates on a parity check matrix of a judiciously designed block structure, which permits low cost hardware implementation, and high encoding throughput.

Method and apparatus for encoding quasi-cyclic low-density parity check codes

In this invention, a new class of finite precision multilevel decoders for low-density parity-check (LDPC) codes is presented. These decoders are much lower in complexity compared to the standard belief propagation (BP) decoder. Messages utilized by these decoders are quantized to certain levels based on the number of bits allowed for representation in hardware. A message update function specifically defined as part of the invention, is used to determine the outgoing message at the variable node, and the simple min operation along with modulo 2 sum of signs is used at the check node. A general methodology is provided to obtain the multilevel decoders, which is based on reducing failures due to trapping sets and improving the guaranteed error-correction capability of a code. Hence these decoders improve the iterative decoding process on finite length graphs and have the potential to outperform the standard floating-point BP decoder in the error floor region. The description and apparatus of 3-bit decoders for column-weight three LDPC codes is also presented.

Low complexity finite precision decoders and apparatus for LDPC codes

A system for soft-decoding of Reed-Muller coded information has one or more rows of decoding blocks, each decoding block having a soft-output device and a Reed-Muller message passing device. A first soft-output device of a first decoding block processes a coded signal and a zero value probability vector. Each subsequent soft-output device processes the coded information and a non-zero value probability vector. The system for soft-decoding Reed-Muller coded information decodes a code-bit reliability vector from a soft-output device to generate an updated codeword reliability vector, which is used by a next decoding block in a sequence of decoding blocks to reprocess the coded information using the updated reliability vector. The reliability vector is updated through processing in each decoding block to optimize the reliability vector for extraction of the transmitted information from the received information.

System and method for iterative decoding of Reed-Muller codes

A method of generating low density parity check codes for encoding data includes constructing a parity check matrix H from balanced incomplete block design (BIBD) in which a plurality B-sets which define the matrix have no more than one intersection point. The parity bits are then generated as a function of the constructed parity check matrix H.

Method and coding apparatus using low density parity check codes for data storage or data transmission

A method of encoding digital information in order to suppress dc includes the steps of receiving a sequence of m message bits of a message word, and mapping the sequence of m message bits of the message word to a codeword, of length n bits, generated from the m message bits using algebraic operations. Multiple codeword candidates are generated from the m message bits using the algebraic operations to combine the m message bits with different periodic scrambling sequences. One of the codeword candidates is selected for mapping based upon an optimizing criteria. Second order digital sum sequences, corresponding to each of the plurality of codeword candidates, can be used as the optimizing criteria to select the codeword.

Method and apparatus for suppressing low frequency content in digital data

The present invention provides a novel method and apparatus for decoding digital information transmitted through the communication channel or recorded on a recording medium. The method and apparatus are preferably applied in the systems where data is encoded using regular LDPC codes with parity check matrices composed from circulants (a matrix is called a circulant if all its column or row are cyclic shifts each other).

Method and decoding apparatus using linear code with parity check matrices composed from circulants

An iterative decoding system for intersymbol interference (ISI) channels has a module for extracting bit reliabilities from a partial response (PR) channel, an iterative decoder, and a module for updating the bit reliabilities. A transmitter parses a data sequence into blocks that are encoded to generate a sequence of codewords. By encoding, a correlation among the bits of each codeword output to the PR channel is created. A maximum likelihood sequence detector (MLSD) in the receiver produces estimates of transmitted bits from samples of the output from the PR channel. The MLSD detector has a priori knowledge of typical error events that can occur during transmission through the channel. Along with the bit estimates, at each time instant the MLSD detector generates set of error event likelihoods. These error event likelihoods are then converted into bit reliabilities that, together with estimates for the transmitted bits, are used to recalculate the bit reliabilities using the knowledge of the relation between bits within a codeword. The iterative decoder uses this soft input information (bit reliabilities and bit estimates) for each iteration of decoding to improve i) the estimate of the bit reliabilities, ii) the decisions of what bit has been transmitted, and iii) calculations for the error event likelihoods for the next iteration. These error event likelihoods are then converted into bit reliabilities that, together with estimates for the transmitted bits, are used by the iterative decoder to recalculate the bit reliabilities using the knowledge of correlation among bits within the codeword. The error event likelihoods may be updated using the updated bit reliabilities, and the updated error event likelihoods are then converted to new bit reliabilities for the next iteration. In an iterative manner, increasing those bit reliabilities that tend to show increasing confidence for corresponding decoded bits (i.e., corresponding Viterbi decisions) between iterations, while decreasing those reliabilities that tend to show decreasing confidence for corresponding decoded bits, tends to drive the iterative decoding scheme to fewer iterations while maintaining a predetermined probability of error.

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Tucson, AZ, United States of America

Bane Vasic