Red Hat, Inc.

Bandan Das

Karen Lee Noel

Michael Tsirkin

Paolo Bonzini

Andrea Arcangeli

Some examples can enable secure and efficient power management of a target hardware device by a virtual machine. For example, a first hypervisor supporting a first virtual machine can receive a first request from the first virtual machine. The first request can indicate a target power mode for the target hardware device assigned to the first virtual machine. In response to receiving the first request, the first hypervisor can transmit a second request indicating the target power mode for the target hardware device to a second hypervisor. The second hypervisor can forward the second request to a second virtual machine, and the second virtual machine can cause the target hardware device to enter the target power mode in response to receiving the second request.

Facilitating power management of a hardware device by a virtual machine

Providing supplemental information to a guest operating system by a hypervisor is disclosed. A hypervisor executing on a host computing device initiates a virtual machine comprising a guest kernel. The hypervisor determines an address of a shared memory area that is accessible by the guest kernel and accessible by the hypervisor. The hypervisor determines that an event has occurred for which supplemental information exists, the event corresponding to a particular event code of a plurality of different event codes. The hypervisor determines a location in the shared memory area that corresponds to the particular event code. The hypervisor inserts the supplemental information at the location in the shared memory area. The hypervisor causes an interrupt of the guest kernel.

Providing supplemental information to a guest operating system by a hypervisor

Processor core power management in a virtualized environment. A hypervisor, executing on a processor device of a computing host, the processor device having a plurality of processor cores, receives from a guest operating system of a virtual machine, a request to set a virtual central processing unit (VCPU) of the virtual machine to a first requested P-state level of a plurality of P-state levels. Based on the request, the hypervisor associates the VCPU with a first processor core having a P-state that corresponds to the first requested P-state level.

Processor core power management in a virtualized environment

Inhibiting memory accesses to executable modules. A hypervisor executing on a computing host initiates a virtual machine comprising a guest operating system. The hypervisor receives a communication from the guest operating system requesting that a range of memory utilized by the guest operating system be identified as being execute-only access. The hypervisor marks at least one physical page of memory that includes the range of memory as being execute-only access.

Inhibiting memory accesses to executable modules

A system and method of emulating virtual processor identifiers includes a nested hypervisor requesting a virtual processor identifier, which identifies a virtual processor, the request triggering an exit to a host hypervisor. The host hypervisor identifies a request including the virtual processor identifier. The host hypervisor generates a key defining an association between a virtual machine and the virtual processor identifier. The host hypervisor stores the key.

Emulating VPID correctly for a nested hypervisor

According to one example, a method includes, with a hypervisor, advertising a paravirtualized cluster mode for a guest using a legacy Advanced Programmable Interrupt Controller (APIC), the paravirtualized cluster mode allowing for interrupts using logical destination mode on a virtual machine having a plurality of virtual cores that is greater than eight. The method further includes, associating each of the plurality of virtual cores with an N-bit identifier formatted to be one of 2different values. The method further includes, with the hypervisor, in response to receiving an interrupt for the virtual machine, determining to which of the plurality of virtual cores the interrupt should be sent based on at least a subset of bits in a destination address of the interrupt.

Paravirtualized cluster mode for legacy APICs

Certain aspects and feature provide a host hypervisor that includes and advertises a virtual machine function that directs the host hypervisor to execute the next job with real-time priorities. A processing device can execute an application in a nested virtual machine, where the application includes at least one code section that relies on or makes use of real-time prioritized resources of the processing device. The processing device recognizes a virtual machine function call in response to the application determining that a code section using real-time prioritized resources is to be executed. The virtual machine function serves as a command that directs a host hypervisor to execute the next job (the next section of code to be executed) with real-time priorities. The processing device executes the code section in a real-time thread in response to the virtual machine function being called.

Command-based processing of real-time virtualized jobs

A method performed by a physical computing system includes, with a hypervisor, determining a first time difference between when pause exiting was last enabled for the virtual machine and present time. The method further includes, with the hypervisor, in response to determining that the first time difference is greater than an enablement threshold, enabling pause exiting. The method further includes, with the hypervisor, with pause loop exiting enabled, determining a second time difference between when pause exiting was last disabled and the present time. The method further includes, with the hypervisor, disabling pause exiting in response to determining that the second time difference exceeds a disablement threshold.

Dynamic pause exiting

Implementing high-performance virtual machines for bare metal simulation is disclosed. A hypervisor executing on a host computer receives a request to initiate a high-performance (HP) virtual machine (VM). The hypervisor selects, based on the request, a HP virtual machine exit (VMEXIT) configuration from a plurality of different VMEXIT configurations. Each respective VMEXIT configuration of the plurality of different VMEXIT configurations identifies VMEXIT behavior in response to a task executing in a VM having a virtual machine control structure (VMCS) generated based on the respective VMEXIT configuration. The hypervisor generates a HP VMCS for the HP VM based on the HP VMEXIT configuration, the HP VMCS controlling the VMEXIT behavior in response to a task executing in the HP VM. The hypervisor initiates the HP VM.

Implementing high-performance virtual machines for bare metal simulation

Controlled use of a memory monitor instruction and memory wait instruction in a virtualized environment. A hypervisor executing on a computing host determines that a first process executing in a virtual machine (VM) attempted to execute a memory monitor instruction. The hypervisor determines a memory range associated with the memory monitor instruction. A virtual machine control structure that corresponds to the VM is altered to prevent a virtual machine exit upon a subsequent execution of a memory wait instruction by the first process. The hypervisor executes the memory monitor instruction to cause the memory range to be monitored for a store command to the memory range. The hypervisor returns control to the first process to begin execution at an instruction after the memory monitor instruction.

Controlled use of a memory monitor instruction and memory wait instruction in a virtualized environment

A controller sandbox using an emulation framework of a hypervisor is disclosed. A hypervisor receives, from a task in a virtual machine that is controlled by the hypervisor in a computing device on which the hypervisor executes, a first implement device command request that requests that a first device command be implemented on a controllable device communicatively connected to the computing device via an interface. The hypervisor determines that the first device command is on an authorized device command list. Based on determining that the first device command is on the authorized device command list, the hypervisor communicates a signal to the controllable device to implement the first device command.

Hypervisor protection of a controllable device

A system and method of exitless extended page table switching includes a nested hypervisor writing pointer addresses to an extended page table list, where each pointer address is associated with an extended page table. The host hypervisor verifies that each pointer address corresponds to a guest physical address for one of the extended page tables. The host hypervisor then creates shadow extended page tables, each of which includes a shadow pointer address corresponding to a host physical address, writes, in a local page table list, each shadow pointer address and an index of each shadow extended page table, and loads the local page table list. The nested guest requests to switch between two extended page tables. The nested guest then identifies a matching entry for an extended page table in the local page table list and switches to the extended page table without triggering an exit.

Exitless extended page table switching for nested hypervisors

Methods, systems, and computer program products are included for switching from a first guest virtual address (GVA)-to-host physical address (HPA) translation mode to a second GVA-to-HPA translation mode. A method includes comparing, by a hypervisor, a number of translation lookaside buffer (TLB) misses to a miss threshold, the hypervisor being in a first GVA-to-HPA translation mode. The method includes switching from the first GVA-to-HPA translation mode to a second GVA-to-HPA translation mode if the number of TLB misses satisfies the miss threshold.

Switching between single-level and two-level page table translations

A system and method of emulating page table modification logging includes a host hypervisor identifying a first mapping in a nested extended page table and identifying a first bit in a first page table entry of the nested extended page table. The host hypervisor creates a second write-protected mapping in a shadow extended page table. The nested guest performs a first write access to a first page in the nested guest. The first page has a first nested guest physical address corresponding to the second mapping. The host hypervisor triggers an exit from the nested guest to the host hypervisor. The host hypervisor identifies that the first write access occurred and stores the first nested guest physical address in a page modification log (PML) buffer of the nested hypervisor. The host hypervisor sets the first bit as a dirty bit and returns to the nested guest.

Emulating page modification logging for a nested hypervisor

Systems and methods for hypervisor scheduling of polling tasks are disclosed. In one implementation, responsive to determining that no input/output (I/O) worker tasks associated with virtual machines are running on a processor of a host computer system running a plurality of virtual machines, callback dispatcher task may be invoked by the processor. The callback dispatcher task may identify an entry of a callback list, wherein the entry references an input/output (I/O) worker task associated with a virtual machine of the plurality of virtual machines. The callback dispatcher task may further invoke a callback code referenced by the entry of the callback list. Responsive to identifying a pending I/O request, the callback code may wake up the input/output (I/O) worker task associated with the entry of the callback list.

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Westford, MA, United States of America

Bandan Das