Lattice Semiconductor Corporation

Sun Microsystems, Inc.

Microunity Systems Engineering, Inc.

Easic Corporation

Ban Pak Wong

John Gray Campbell

Brad Sharpe-Geisler

Hui Hui Ngu

Yoganand Chillarige

Shivakumar Sompur

Sanjay Dubey

Cynthia Tran

In one embodiment, a ball grid array (BGA) of a packaged semiconductor device and a corresponding landing pad array of a printed circuit board each have a layout defined by an interconnection array having (i) an inner sub-array of locations having connectors arranged in rows and columns separated by a specified pitch and (ii) an outer rectangular ring of locations having connectors arranged in rows and columns separated by the specified pitch. The outer rectangular ring is separated from the inner sub-array by a depopulated rectangular ring having a width of at least twice the specified pitch, wherein the depopulated rectangular ring has no connectors. The outer rectangular ring has empty locations having no connectors. Some of those empty locations define depopulated sets that divide the outer rectangular ring into a number of different contiguous sets of locations having connectors that enable pin escape for connectors of the device's BGA.

Partially depopulated interconnection arrays for packaged semiconductor devices and printed circuit boards

A bitline structure for use in a memory device may be connected to a plurality of bit memory cells. The bitline may be segmented into segments connected to one-third of the plurality of bit memory cells and two-thirds of the bit memory cells, respectively. The segments may be electrically coupled to each other to provide an overall bitline output.

ROM segmented bitline circuit

A ball-grid-array (BGA) package is disclosed that includes traces within a BGA substrate. At least one of the traces is configured to match a low-impedance load presented by a BGA substrate pad and associated circuitry on a flip-chip die to an impedance of a circuit board trace. Each configured trace includes a relatively narrow section coupling to a tapered section that widens from the relatively narrow section to join a relatively wider trace section.

Integrated circuit package with input capacitance compensation

An arithmetic logic unit (ALU) implemented with complementary pass gate logic using propagate, generate, and kill is provided. Broadly speaking, the ALU is a 64-bit ALU using a multi-stage global carry chain to generate intermediate fourth-bit carries that are folded with local four-bit sums to efficiently generate a final sum output. The ALU implements ones complement subtraction by incorporating a subtraction select signal to invert each bit of a second operand. The ALU circuitry implements a push-pull methodology to improve performance.

Complementary pass gate logic implementation of 64-bit arithmetic logic unit using propagate, generate, and kill

A method for reducing sub-threshold leakage during the burn-in procedure for a semi-conductor is disclosed. The method includes applying a back-bias voltage to the device during the burn-in procedure. The back-bias voltage increases the threshold voltage of the semi-conductor device and consequently, reduces the sub-threshold leakage current.

Method to reduce leakage during a semi-conductor burn-in procedure

An output buffer that controls the slew rate of its output signal is disclosed. The buffer includes a pull-up and a pull-down bipolar transistor coupled at a common output node in series between VDD and VSS. The buffer also includes a first set of parallel MOS devices coupled between the common output node and the base of the pull-down bipolar transistor. A second set of parallel MOS devices are coupled between the base of the pull-up output stage bipolar transistor and VDD. The gates of each set of MOS devices are coupled to a digital select signal. The amount of current driving the base of each of the pull-up and pull-down transistors (when they are enabled) is determined by the number of MOS devices enabled by the digital select signal. Thus, the buffer of the present invention is able to adjust the slew rate of its output signal to accommodate different loads coupled to the common output node.

Controlled slew rate output buffer

A current mode access BiCMOS memory cell is disclosed. The memory cell includes a CMOS storage cell for storing first and second CMOS voltage potentials, VDD and VSS, corresponding to first and second logic levels. The storage cell includes two CMOS inverters coupled between VDD and VSS. The storage cell is coupled to a conversion circuit. The conversion circuit is coupled between third and fourth ECL working potentials. It functions to convert the first and second CMOS voltage potentials into the third and fourth working potentials. The third and fourth voltage potentials are coupled to the bases of two bipolar signal converters. The emitters of the bipolar signal converters are coupled to a selectable current source and the collectors of the bipolar signal converters are coupled to complementary bit lines. The selectable current source is responsive to a read word signal. A differential current signal representing the data stored in the memory cell is established in the complementary bit lines when the current source is selected and current is allowed to flow through one of the bipolar signal converters. The third and fourth ECL voltage potentials are chosen such that they ensure that the bipolar signal converters are not driven into saturation. In this way, read times are optimized. In addition, read times are reduced since peak-to-peak voltage of the current mode differential signal established across the complementary bit lines are reduced.

Growing community of inventors

Milpitas, CA, United States of America

Ban Pak Wong