Stmicroelectronics Pvt. Ltd.

Stmicroelectronics International N.v.

Balwant Singh

Swapnil Bahl

Saurabh Kumar Singh

Ruchir Saraswat

Prashant Dubey

Naveen Tiwari

Narayanan Vijayaraghavan

Hina Mushir

Vijayaraghavan Narayanan

A test circuit measures both the rising edge delay and the falling edge delay associated with a logic cell. The test circuit includes a flip-flop type ring oscillator with two groups of logic cells connected in series in the oscillation path. A first multiplexor switches the ring oscillator between a rising edge and a falling edge mode. A second multiplexer causes the second group of logic cells to be included or excluded from the oscillation path. By measuring the oscillation period in the various modes, the rising edge and falling edge delays can be individually calculated.

Scheme to measure individually rise and fall delays of non-inverting logic cells

The present invention provides a flexible on-chip testing circuit and methodology for measuring I/O characterization of multiple I/O structures. The testing circuit includes a register bank, a central processing controller (CPC), a character slew module, a delay characterization module, and a character frequency module. The register bank stores multiple instructions, and measurement results. The CPC fetches the instructions from the register bank. The CPC includes various primary and secondary state machines for interpreting the fetched instructions for execution. Depending on the input instruction the CPC applies stimulus to the IUT and the output of the IUT is used by the Local characterization modules (CHARMODULE) to extract the desired characterization parameters such as the character slew module which measures a voltage rise/fall time either for a single voltage IUT or a multi-voltage IUT. The Test Methodology for STIOBISC consists of an automated ATE pattern generation from verification test benches and automated result processing by converting the ATE data logs into the final readable format, thereby considerably reducing the test setup and output processing time. The testing circuit can operate in multiple modes for selecting one of these modules.

Flexible on chip testing circuit for I/O's characterization

A circuit for measuring maximum operating frequency and its corresponding duty cycle for an input I/O cell implementation under test (IUT) includes a condition checking module, a central control module and a duty cycle measurement module. The condition checking module checks an upper threshold voltage and a lower threshold voltage. The central control module controls a plurality of operations for measuring the frequency. The duty cycle measurement module measures the duty cycle and finally all these modules together and calculates maximum operating frequency of the IUT.

Method and system for measuring maximum operating frequency and corresponding duty cycle for an I/O cell

A system and method for providing improved resolution in the measuring the pulse width of digital signals comprising counting the integral number of measuring clock pulses covered by said digital pulse and triggering a chain of cascaded high resolution delay elements from the trailing edge of said measuring clock pulses. Further, the invention measures the delay count obtained from said chain of cascaded delay elements from the trailing edge of the last measuring clock pulse up to the end of said digital pulse, and adds said measured delay count to said integral measuring clock pulse count to obtain the total width of said digital pulse.

Resolution in measuring the pulse width of digital signals

An improved on-chip storage memory and method for storing variable data bits, the memory including an on-chip storage memory system for storing variable data bits that has a memory for storing data bits, a wrapper for converting the memory into a first-in first-out (FIFO) memory, and a controller for performing operations on the memory. In operation, the memory is converted into a FIFO memory after storing data, and output logic selects data to be output in a serial manner.

On-chip storage memory for storing variable data bits

An on-chip and at-speed tester for testing and characterization of different types of memories in an integrated circuit device, comprising a Centralized Flow Controller for automatically controlling the test operations for selected test programs, and Localized Signal Generators located inside each memory block and controlled by said Centralized Flow Controller for applying specified test patterns on the associated memory array.

On-chip and at-speed tester for testing and characterization of different types of memories

A glitch free controlled ring oscillator may comprise a programmable delay chain connected to a gating and inverter stage or means. A latch or latching means may be provided between the delay chain and the gating and inverter stage or means for registering the clock state at the time of disabling the oscillator and setting the output of the oscillator to the registered clock state.

Glitch free controlled ring oscillator and associated methods

A configurable length first-in first-out (FIFO) memory includes a memory core for storing data, a write address counter connected to the memory core for counting locations for writing the data to be stored, and a read address counter connected to the memory core for counting the locations for reading the stored data. The read address counter includes a comparator for generating a synchronous reset for itself. A selector is connected to the comparator for selecting a user defined FIFO length, or a pre-programmed write address counter length.

Configurable length first-in first-out memory

An apparatus for enabling the on-chip analysis of the voltage and/or current transition behaviour of one or more embedded nets of an integrated circuit independently of the fabrication process. The said apparatus comprises a Reference Step Generator (RSG) for providing programmable reference voltages or currents, a Step Delay Generator (SDG) for providing programmable delays, a Comparator (C) that receives the output of the reference step generator on one input, the output from the node under test at the second input, and a latch enable signal from the step delay generator, and provides a latched digital output in response to the comparison, and a controller that co-ordinates the operation of the reference step generator, Step Delay Generator and Latching Comparator to provide a transient response measurement.

On-chip analysis and computation of transition behavior of embedded nets in integrated circuits

A digital circuit operating frequency characterizer provides a combination of frequency and duty cycle characterization. The digital circuit operating frequency characterizer includes a programmable frequency generator, a programmable edge variator, a test engine, and a control circuit. The programmable frequency generator provides one or more output signals, and the programmable edge variator is coupled to one or more outputs of the programmable frequency generator for adjusting duty cycle. The test engine uses the outputs from the programmable edge variator and/or programmable frequency generator to apply a defined test signal sequence to a circuit under test and produce a status output after evaluating the outputs received from the circuit under test. The control circuit is connected to the control inputs of the programmable frequency generator, programmable edge variator, and the status output of the test engine. The control circuit synchronizes their operations and performs the combination of frequency and duty cycle characterization.

Digital circuit for frequency and timing characterization

A system for measuring a timing skew between two digital signals may include a clock generator for generating a time measurement clock, and a pulse-to-digital converter for converting the timing skew into an equivalent digital coded value after correcting for internal logic delays. The system may further include a register bank for storing the digital coded values, and a controller for generating control signals and sequences for controlling the operation of the pulse-to-digital converter and the register bank.

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Greater Noida, India

Balwant Singh