Cadence Design Systems, Inc.

Balvinder Singh

Taranjit Singh Kukal

Arnold Jean Marie Gustave Ginetti

Madhur Sharma

Ritabrata Bhattacharya

Arnold Ginetti

Donald John O'Riordan

Devendra Ramakant Deshpande

Steven Roberts Durrill

Nikhil Gupta

Vikrant Khanna

Bogdan George Arsintescu

Sutirtha Kabir

Vikas Aggarwal

Claudia Ursula Roesch

Murray Glen Shattuck, Jr

Jagdish Lohani

Michael Thompson

Harmohan Singh

Diwakar Mohan

Abhishek Dabral

Alka Goel

Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving, using at least one processor, an electronic design layout and performing parasitic extraction on the electronic design layout. Embodiments may further include extracting an electromagnetic model from the electronic design layout and reconnecting at least one coupling capacitor associated with a net of the electromagnetic model. Embodiments may include performing a simulation including the reconnected at least one coupling capacitor.

System and method for electromagnetic modeling in an electronic circuit design

Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with a schematic driven extracted view. These techniques identify a schematic of an electronic design, wherein the schematic exists in one or more design fabrics. These techniques further determine an extracted model for characterizing a behavior of the electronic design based at least in part upon the schematic, determine a hierarchical level in a design fabric of the one or more design fabrics of the schematic, and characterize the electronic design with at least an extracted view.

Methods, systems, and computer program product for characterizing an electronic design with a schematic driven extracted view

Various embodiments provide for partial selection-based (e.g., cut-based) model extraction from a layout of a circuit design, which can be used to generate a schematic extracted view for the circuit design and to back annotate a schematic of the circuit design. For some embodiments, the selection comprises a cut of a layout of a circuit design, where the cut may be defined (e.g., inputted) by a user through a graphical user interface that is presenting the layout.

Partial selection-based model extraction from circuit design layout

Embodiments include herein are directed towards a method for use in an electronic design environment is provided. The method may include providing, using at least one processor, an electronic circuit design including an integrated circuit ('IC') or package schematic and generating a power distribution network ('PDN') based upon at least in part, the electronic circuit design including the IC or package. The method may further include obtaining a PDN model having one or more port mappings between one or more layout terminals and one or more schematic pin-names and stitching the PDN model and the IC or package schematic into a combined PDN and IC or package schematic model. The method may also include simulating the combined PDN and IC or package schematic model using the at least one processor.

System and method for power-grid aware simulation of an IC-package schematic

Disclosed are methods, systems, and articles of manufacture for binding and annotating an electronic design with a schematic driven extracted view. These techniques identify a schematic design and an extracted view of an electronic design and bind the schematic design with the extracted view. The resulting binding information concerning binding the schematic design with the extracted view is stored in a data structure. The schematic design may be annotated with extracted view information pertaining to the extracted view based at least in part upon the binding information. A response to a user action may be automatically generated based in part or in whole upon the extracted view information or the binding information.

Methods, systems, and computer program product for binding and back annotating an electronic design with a schematic driven extracted view

Disclosed are methods, systems, and articles of manufacture for implementing schematic driven extracted views for an electronic design. These techniques identify a schematic circuit component design represented by a schematic symbol from a schematic design and identifying layout device information from a layout of the electronic design. An extracted view is generated anew or updated from an existing extracted view at least by placing and interconnecting a symbol in the schematic design based at least in part upon the layout device information. The electronic design may be further updated based in part or in whole upon results of performing one or more analyses on the extracted view.

Methods, systems, and computer program product for implementing schematic driven extracted views for an electronic design

Disclosed are techniques for implementing a layout-driven, multi-fabric schematic design of an electronic design. These techniques identify a multi-fabric layout spanning across multiple design fabrics and layout connectivity information and determine a device map that correlates a first set of devices in the multi-fabric layout with respective parasitic models. The device map can be identified one or more pre-existing device maps or can be constructed anew. A multi-fabric schematic can be generated by using at least the respective parasitic models and the layout connectivity information.

Methods, systems, and computer program product for implementing a layout-driven, multi-fabric schematic design

The present invention provides a system and method for generating circuit schematic that includes extracting connectivity data of a plurality of devices from a netlist, categorizing the plurality of devices into groups, placing Schematic Analog Placement Constraints on all the instances by identifying instances among the groups that match with a circuit template (in-built as well as user-specified), creating a BFS instance tree of tree instances, creating a two terminal device clusters and creating instance attachments. Using the constraints during grid based placement and eventually generated schematic which look like analog schematic.

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Faridabad, India

Balvinder Singh