Intel Corporation

Balkaran Gill

Norbert Roland Seifert

Suraj Sindia

Clark N Vandam

Ketul B Sutaria

Suriya Suriya Ashok Kumar

Junho Song

Kasyap Pasumarthi

Robert F Kwasnick

Santosh Ghosh

Harry Muljono

Zhen Yao

Jose A Maiz

Tamir Damian Munafo

Xiaofeng Yang

Mariano J Phielipp

Avner Kornfeld

Randy L Allmon

Lital Shiryan

Sanjay Joshi

Shah M Jahinuzzaman

Raj Singh Dua

An on-die early lifetime failure detection system with a reliability mechanism isolation circuit provides an early lifetime failure detection. The system measures and monitors reliability at time-0 (t0) and end-of-life. The measurements enable detection of latent reliability or marginality issues during the lifetime of the product. The system includes: a stress controller to adjust voltage for a power supply and voltage for a ground supply in accordance with one or more sensors; and an aging detector circuitry coupled to the stress controller, wherein the aging detector circuitry comprises a ring oscillator having delay stages, wherein each delay stage comprises an aging monitor circuitry, wherein the stress controller to adjust voltage for a power supply and voltage for a ground supply of the delay stage.

Apparatus and method for early lifetime failure detection system

Analog Front End (AFE) driver or transmitter is used for ESD protection of an input-output (IO) pin, thus reducing ESD diode count and subsequently lowering the pad capacitance to achieve high performance in IO circuits like double data rate (DDR) IO, PCI Express (Peripheral Component Interconnect Express), etc. The channel of active devices that constitute AFE driver are used to connect an IO pad to discharge the ESD current to ground, thus providing an alternative path to ESD current and subsequently reducing the ESD diode count. An additional p-type device (Driver Path Enabler (DPE)) is coupled between the IO pad and a gate terminal of the AFE driver. This additional p-type device triggers the channel of the AFE driver. This p-type device is controlled by an RC based structure which cuts the p-type device off during regular operations when power is ramped-up.

Driver assisted ESD protection apparatus and method

An apparatus is described having a latch circuit. The latch circuit includes redundant data inputs, redundant data outputs, redundant clock inputs and circuitry to self-correct a soft-error.

Latch with redundancy and circuitry to protect against a soft error

A self-adaptive security framework for a device is disclosed. A first security level for a device is set wherein the first security level comprises procedures that authenticate a user and allow the user to access the device. Input from sensors associated with the device may be received at a contextual sensing engine, wherein the input at least includes location data, and wherein at least a portion of the input is related to a physical setting where the device is located. A threat level for the device is determined in the physical setting via the contextual sensing engine based on analyzing the input. The first security level is altered to a second security level to provide an altered threat response for the device based on the threat level wherein the second security level has different procedures to authenticate the user compared to the first security level.

Self-adaptive security framework

An apparatus and method are described for an on-chip reliability controller. For example, one embodiment of a processor comprises: a set of one or more cores to execute instructions and process data; a reliability controller to perform one or more self-test/diagnostic operations, the reliability controller to aggregate reliability data resulting from the self-test/diagnostic operations; a reliability estimator integral to the reliability controller to use the aggregated reliability data to perform a probability analysis to determine reliability estimates for one or more components of the processor; and a control unit integral to the reliability controller to adjust one or more variables and/or circuitry related to operation of the processor responsive to the reliability estimates.

Apparatus and method for an on-chip reliability controller

Technologies for detecting a physical assault against a user include one or more clothing sensor modules coupled to a garment of the user. Each clothing sensor module is configured to produce sensor data indicative of the removal of the garment from the user and determine whether a physical assault is presently occurring against the user using an assault detection model with the sensor data as an input to the assault detection model. In response to a determination of the physical assault against the user, the clothing sensor module is configured to alert a trust party.

Technologies for physical assault detection using secure clothing and/or clothing accessories

Apparatus, method, and system for remotely affecting the functionality and lifetime of an integrated circuit are described herein. One embodiment of a method includes: tracking a plurality of operational metrics relating to a monitored device, sending one or more of the plurality of operational metrics to a remote monitor and responsively receiving a command generated by the remote monitor, generating a threat level based on the plurality of operational metrics and the command, and performing a derating action based on the threat level. The command from the remote monitor may be generated by the remote monitor based, at least in part, on the one or more of the plurality of operational metrics. Alternatively, the command may be generated based on information obtained independently by the remote monitor and not based on the one or more of the plurality of operational metrics.

Architecture for telemetry and adaptive lifetime control of integrated circuits

Described is a processor comprising: a plurality of radiation detectors; a first logic unit to receive outputs from the plurality of radiation detectors, the logic unit to generate an output according to the received outputs, the output of the first logic unit indicating whether the processor was exposed to incoming radiations; and a second logic unit to receive the output from the first logic unit, and to cause the processor to perform an action according to the output from the first logic unit.

High dose radiation detector

A latch is provided that includes a first inverter, a second inverter, a first latch circuit and a second latch circuit. The first inverter to receive the first clock signal from an input port and to provide a clock signal. The second inverter to receive the first clock signal from the input port and to provide a clock signal. The first latch circuit is to store data and to receive a clock signal from the second inverter. The second latch circuit is further to store data and to receive a clock signal from the first inverter.

Soft error rate hardened latch

Various embodiments include a latch having a node to receive input information, and a first pseudo-inverter with a first input node, a second input node, and an output node to generate output information based on information at the first and second input nodes. The latch may have a feedback circuit to generate feedback information based on at least the output information. The latch may also have a select circuit to selectively transfer the input information and the feedback information to the first and second input nodes. Other embodiments including additional apparatus, systems, and methods are disclosed.

Growing community of inventors

Cornelius, OR, United States of America

Balkaran Gill