Intel Corporation

Micron Technology Incorporated

Sun Microsystems, Inc.

Balint Fleischer

Debendra Das Sharma

Mohan J Kumar

Robert G Blankenship

Mark A Schmisseur

Raj K Ramanujan

Kenneth C Creta

Brian S Morris

Michelle C Jen

Suresh Rajgopal

Suresh S Chittor

A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.

Sharing memory and I/O services between nodes

A first die has a port to couple the first die to a second die over a die-to-die interconnect. The port includes circuitry to implement a physical layer of the die-to-die interconnect, send first protocol identification data over the physical layer to identify a first protocol in a plurality of protocols, send first data over the interconnect to the second die, wherein the first data comprise data of the first protocol, send second protocol identification data over the physical layer to identify a different second protocol in the plurality of protocols, and send second data over the interconnect to the second die, wherein the second data comprise flits of the second protocol.

An apparatus includes a memory component having a plurality of ball grid array (BGA) components, wherein each respective one of the BGA components includes a plurality of memory blocks and a BGA component controller and firmware adjacent the plurality of memory blocks to manage the plurality of memory blocks. The apparatus further includes a processing device, included in the memory component, to perform memory operations on the BGA components.

Ball grid array storage for a memory sub-system

Provided are a method, system, computer readable storage medium, and switch for configuring a switch to assign partitions in storage devices to compute nodes. A management controller configures the switch to dynamically allocate partitions of at least one of the storage devices to the compute nodes based on a workload at the compute node.

Method and apparatus for dynamically allocating storage resources to compute nodes

An apparatus for providing data coherency is described herein. The apparatus includes a global persistent memory. The global persistent memory is accessed using a protocol that includes input/output (I/O) semantics and memory semantics. The apparatus also includes a reflected memory region. The reflected memory region is a portion of the global persistent memory, and each node of a plurality of nodes maps the reflected memory region into a space that is not cacheable. Further, the apparatus includes a semaphore memory. The semaphore memory provides a hardware assist for enforced data coherency.

Data coherency model and protocol at cluster level

An apparatus for coherent shared memory across multiple clusters is described herein. The apparatus includes a fabric memory controller and one or more nodes. The fabric memory controller manages access to a shared memory region of each node such that each shared memory region is accessible using load store semantics, even in response to failure of the node. The apparatus also includes a global memory, wherein each shared memory region is mapped to the global memory by the fabric memory controller.

Assisted coherent shared memory

An apparatus for pooling memory resources across multiple nodes is described herein. The apparatus includes a shared memory controller, wherein each node of the multiple nodes is connected to the shared memory controller. The apparatus also includes a pool of memory connected to the shared memory controller, wherein a portion of the pool of memory is allocated to each node of the multiple nodes.

Pooling of memory resources across multiple nodes

A digital data transfer system transfers digital data along a path in a ring topology. The digital data transfer system comprising a host controller and a digital data transfer subsystem. The host controller generates and receiving digital data and the digital data transfer subsystem receives the digital data from the host controller and transferring the digital data to one or more devices connectable thereto, and further receives digital data from the last of the devices connectable thereto for provision to the host controller, thereby to define the ring data transfer topology. The digital data transfer subsystem comprises an upstream port, a plurality of input/output ports and a port control. The upstream port transfers digital data from an external source to the input of the first input/output port in the series and transfers digital data received from the last input/output port in the series to the host controller. Each input/output port includes a port input terminal, a port output terminal, a device output port, a device input terminal, and an output data selector. The input/output ports are connected in series such that the port input terminal of the first input/output port in the series receives data from the upstream port, the port output terminal of the last input/output port in the series provides data to the upstream port, and the port output terminal of each of the other input/output ports in the series provides data to the port input terminal of the next input/output port in the series. Each input/output port couples data from its port input terminal to its device output terminal thereby to provide data received at its port input terminal to a device which may be connected thereto, and coupling data from its device input terminal to its respective output data selector. The output data selector of each input/output port is further connected to receive data from the respective port input terminal, the output data selector selectively coupling data from one of the port input terminal or the device input terminal to the input/output port's output terminal. The port control controls the output data selector of each the input/output port in response to a determination as to whether a respective device is connected thereto.

Growing community of inventors

Groton, MA, United States of America

Balint Fleischer