International Business Machines Corporation

Globalfoundries Inc.

Adeia Semiconductor Bonding Technologies Inc.

Stmicroelectronics Gmbh

Lam Research Corporation

Elpis Technologies Inc.

Adeia Semiconductor Solutions LLC

Globalfoundries U.S. Inc.

Samsung Electronics Co., Ltd.

Balasubramanian Pranatharthiharan

Injo Ok

Ruilong Xie

Soon-Cheon Seo

Kangguo Cheng

Andrew Mark Greene

Charan V V S Surisetty

Charan V Surisetty

Shom Ponoth

Junli Wang

Hui Zang

Sanjay C Mehta

Huiming Bu

Alexander Reznicek

Tenko Yamashita

Nicolas J Loubet

Sivananda K Kanakasabapathy

Lawrence Alfred Clevenger

John Ryan Sporre

Brent A Anderson

Zhenxing Bi

David V Horak

John H Zhang

Julien Frougier

Terence B Hook

Takeshi Nogami

Muthumanickam Sankarapandian

Wei Wang

Chun-chen Yeh

Su Chen Fan

Emre Alptekin

Pietro Montanini

Randolph F Knarr

Bruce Bennett Doris

Juntao Li

Dechao Guo

Michael A Guillorn

Xiuyu Cai

Praneet Adusumilli

Roy Rongqing Yu

Kevin W Brew

Vimal Kumar Kamineni

Myung-Hee Na

Theodorus E Standaert

Chanro Park

Shogo Mochizuki

Oleg Gluschenkov

Lars W Liebmann

Damon B Farmer

Pranita Kulkarni

Joshua M Rubin

George Stojan Tulevski

Rajasekhar Venigalla

Nicole A Saulnier

Huimei Zhou

James John Kelly

Albert M Young

Mark V Raymond

Ali Khakifirooz

Veeraraghavan S Basker

Xin Miao

Mukta G Farooq

Son Van Nguyen

Qing Liu

Ruqiang Bao

Christian Lavoie

Hiroaki Niimi

Ravikumar Ramachandran

Kisik Choi

Renee Tong Mo

Pranita Kerber

Steven J Bentley

Eric R Miller

Richard Anthony Conti

Michael P Belyansky

Mahadevaiyer Krishnan

Jody Alan Fronheiser

Prasanna Khare

Sunfei Fang

Jay William Strane

Mickey H Yu

Chih-Chao Yang

Ghavam G Shahidi

Jeffrey W Sleight

Keith E Fogel

Josephine B Chang

Hemanth Jagannathan

Judson Robert Holt

Christopher J Penny

Oscar Van Der Straten

Thomas N Adam

Nicholas Anthony Lanzillo

Gauri V Karve

Albert Manhee Chu

Stuart A Sieg

John Christopher Arnold

Rishikesh Krishnan

Gen Tsutsui

Jin Wook Lee

Somnath Ghosh

Embodiments of the invention include vertically stacked field-effect transistors (FETs). The vertically stacked FETs include at least one first transistor and at least one second transistor separated by a dielectric isolation layer. Gate material is adjacent to the at least one first transistor and the at least one second transistor, at least one first height vertical layer being adjacent to and about a height of the gate material, at least one second height vertical layer being adjacent to and less than the height of the gate material.

Gate-cut and separation techniques for enabling independent gate control of stacked transistors

A method is presented for reducing a reset current for a phase change memory (PCM). The method includes forming a bottom electrode, constructing a PCM cell structure including a plurality of phase change memory layers and a plurality of heat transfer layers, wherein the plurality of phase change memory layers are assembled in an alternating configuration with respect to the plurality of heat transfer layers, and forming a top electrode over the PCM cell structure. The plurality of phase change memory layers are arranged perpendicular to the top and bottom electrodes. Additionally, airgaps are defined adjacent the PCM cell structure.

Phase change memory using multiple phase change layers and multiple heat conductors

A semiconductor structure is provided that includes a first FET device stacked over a second FET device, wherein the first FET device contains a first functional gate structure containing a first work function metal and the second FET device contains a second functional gate structure containing a second work function metal. In the structure, the first work function metal is absent from an area including the second work function metal, and vice versa. Thus, no shared work functional metal is present in the semiconductor structure.

Stacked FETS with non-shared work function metals

A device comprises a first interconnect structure, a second interconnect structure, a first cell comprising a first transistor, a second cell comprising a second transistor, a first contact connecting a source/drain element of the first transistor to the first interconnect structure, and second contact connecting a source/drain element of the second transistor to the second interconnect structure. The first cell is disposed adjacent to the second cell with the first transistor disposed adjacent to the second transistor. The first and second cells are disposed between the first and second interconnect structures.

Backside power rails and power distribution network for density scaling

The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.

Minimizing shorting between FinFET epitaxial regions

A method of forming a semiconductor structure includes forming a first middle-of-line (MOL) oxide layer and a second MOL oxide layer in the semiconductor structure. The first MOL oxide layer including multiple gate stacks formed on a substrate, and each gate stack of the gate stacks including a source/drain junction. A first nitride layer is formed over a silicide in the first MOL oxide layer. A second nitride layer is formed. Trenches are formed through the second nitride layer down to the source/drain junctions. A nitride cap of the plurality of gate stacks is selectively recessed. At least one self-aligned contact area (CA) element is formed within the first nitride layer. The first MOL oxide layer is selectively recessed. An air-gap oxide layer is deposited. The air gap oxide layer is reduced to the at least one self-aligned CA element and the first nitride layer.

Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack

A semiconductor device includes a first stack of nanowires above a substrate with a first gate structure over, around, and between the first stack of nanowires and a second stack of nanowires above the substrate with a second gate structure over, around, and between the second stack of nanowires. The device also includes a first source/drain region contacting a first number of nanowires of the first nanowire stack and a second source/drain region contacting a second number of nanowires of the second nanowire stack such that the first number and second number of contacted nanowires are different.

Stacked transistors with different channel widths

A semiconductor device including a substrate; a continuous buried oxide layer (BOX) formed on the substrate; and a plurality of nanosheet gate-all-round (GAA) device structures on the BOX, wherein a first plurality of stacked gates of the nanosheet GAA device structures are disposed in a logic portion of the substrate and have a first nanosheet width, wherein a second plurality of stacked gates of the nanosheet GAA device structures are disposed in a high density region of the substrate and have a second nanosheet width less than the first nanosheet width, wherein the nanosheet GAA device structures are disposed directly on the continuous buried oxide layer, and wherein a bottom layer of the nanosheet GAA device structures is a bottom gate formed directly on the BOX.

Stacked nanosheet gate-all-around device structures

A semiconductor device includes a dielectric isolation layer, a plurality of gates formed above the dielectric isolation layer, a plurality of source/drain regions above the dielectric isolation layer between the plurality of gates, and at least one contact placeholder for a backside contact. The at least one contact placeholder contacts a bottom surface of a first source/drain region of the plurality of source/drain regions. The semiconductor device further includes at least one backside contact contacting a bottom surface of a second source/drain region of the plurality of source/drain regions, and a buried power rail arranged beneath, and contacting the at least one backside contact.

Backside electrical contacts to buried power rails

A method of manufacturing a semiconductor device is provided. The method includes forming a first recess partially through a substrate from a first side of the substrate, forming a dielectric layer in the first recess, forming a second recess partially through the dielectric layer from the first side of the substrate, and forming a buried power rail (BPR) in the second recess of the dielectric layer. The method also includes thinning the substrate from a second side of the substrate to a level of the dielectric layer, the second side of the substrate being opposite to the first side of the substrate.

Substrate thinning for a backside power distribution network

A semiconductor structure includes a power distribution network including a first buried power rail, a power wire, and a first buried via electrically interconnecting the first buried power rail and the power wire. Each of the first buried power rail, the power wire, and the first buried via have a liner on a corresponding bottom surface thereof and sidewalls thereof. The structure also includes a dielectric layer outward of the power distribution network; a first field effect transistor outward of the dielectric layer; a first via trench contact electrically interconnecting a source/drain region of the transistor to the first buried power rail; a first outer wire outward of the first field effect transistor; and an electrical path electrically interconnecting the first outer wire with the power wire.

Semiconductor device with early buried power rail (BPR) and backside power distribution network (BSPDN)

A method of fabricating a semiconductor device comprises forming backside power rails in a dielectric layer arranged above a backside interlayer dielectric (BILD) layer or a semiconductor layer, forming a trench that extends through the BILD layer or the semiconductor layer and partly through the dielectric layer between the backside power rails, depositing a plurality of layers to form a backside metal-insulator-metal (MIM) capacitor in the trench, and forming a first contact to a first metal layer of the plurality of layers. Forming the first contact comprises forming first recesses in a second metal layer of the plurality of layers, and filling the first recesses with an insulative material. The method further comprises forming a second contact to the second metal layer. Forming the second contact comprises forming second recesses in the first metal layer, and filling the second recesses with the insulative material.

Backside metal-insulator-metal (MIM) capacitors extending through backside interlayer dielectric (BILD) layer or semiconductor layer and partly through dielectric layer

A semiconductor structure including a first dielectric layer comprising a first conductive metal feature embedded in the first dielectric layer; and a second dielectric layer including a second conductive metal feature embedded in the second dielectric layer, the second conductive metal feature is above and directly contacts the first conductive metal feature, and an interface between the second conductive metal feature and the second dielectric layer includes a repeating scallop shape along its entire length.

Semiconductor structure having alternating selective metal and dielectric layers

A method of manufacturing a semiconductor device is provided. The method includes forming a first trench partially through a first substrate from a first side of the first substrate. The method also includes widening a bottom portion of the first trench to form a lateral footing area of the first trench. The method includes forming a first metallization in the first trench; forming a second trench through a second substrate from a second side of the second substrate to expose at least a portion of first metallization in an area corresponding to the lateral footing area of the first trench, the second side being opposite to the first side. The method also includes forming a second metallization in the second trench in contact with the first metallization.

Backside power rail integration

A semiconductor fabrication method that uses a graphene etch stop is disclosed. The method comprises forming a first set of trenches and a second set of trenches in a substrate. The first set of trenches are narrower than the second set of trenches. The method further comprises forming a graphene layer in the first and second sets of trenches. The method further comprises depositing a first conductor in the first and second sets of trenches. The method further comprises removing the first conductor from the second set of trenches using an etching process. The graphene layer acts as an etch stop for the etching process. The method further comprises depositing a second conductor in the second set of trenches. The second conductor is different than the first conductor.

Composite interconnect formation using graphene

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Watervliet, NY, United States of America

Balasubramanian Pranatharthiharan