International Business Machines Corporation

Balaram Sinharoy

Ravi Kumar Arimilli

Bryan J Lloyd

Ronald Nick Kalla

Dung Q Nguyen

Xiaowei Shen

Hanhong Xue

Chulho Kim

Robert Sidney Blackmore

Joel Abraham Silberman

Hung Qui Le

Bruce Gerard Mealey

David S Levitan

Robert Brett Tremaine

Richard James Eickemeyer

Lixin Zhang

Peter H Hochschild

William Evan Speight

William Elton Burky

Michael K Gschwind

Michael Stephen Floyd

Robert William Wisniewski

Brian William Thompto

Rama Krishna Govindaraju

Satya Prakash Sharma

Shih-Hsiung Stephen Tung

Christopher J Gonzalez

John Wesley Ward, Iii

Ramakrishnan Rajamony

Orran Yaakov Krieger

William John Starke

Lakshminarayana Baba Arimilli

William Joseph Armstrong

Jose Eduardo Moreira

Cathy May

Hazim Shafi

John Barry Griswell, Jr

Minh Michelle Quy Pham

Bulent Abali

Brian David Barrick

Gregory William Alexander

Juan C Rubio

Richard William Doing

Pradip Bose

Silvia Melitta Mueller

Ronald P Hall

Patrick Joseph Bohrer

Mohit Karve

Brian Robert Mestan

Larry Scott Leitner

Gheorghe Calin Cascaval

Benjamin W Stolt

Jeffrey Richard Summers

Jaehyuk Huh

Guy L Guthrie

John Steven Dodson

Alper Buyuktosunoglu

James Allan Kahle

Naresh Nayar

Bruce Martin Fleischer

Peter Kenneth Szwed

Susan Elizabeth Eisen

Elmootazbellah Nabil Elnozahy

Lee Evan Eisen

Bradly George Frey

Raul Esteban Silvera

Mauricio J Serrano

Jude A Rivers

Steven J Battle

Victor V Zyuban

Edward John Silha

Krishnan Kunjunny Kailas

James Wilson Bishop

Moinuddin K Qureshi

Robert Alan Philhower

Tu-An T Nguyen

Nicholas R Orzol

Mehul N Patel

Raymond Cheung Yeung

Joachim Gerhard Clabes

Eric Jason Fluhr

Kevin Neal Magill

Dilma Menezes Da Silva

Zhigang Hu

Scott Bruce Frommer

Ophir Erez

Michael G Rosenfield

Robert William Hay

Douglas Robert Logan

Philip George Emma

Bartholomew Blaner

Richard Louis Arndt

Kailash Gopalakrishnan

Kenneth Lee Wright

Steven Wayne White

Ahmed Gheith

Maarten Jakob Boersma

Albert James Van Norstrand, Jr

Alexander Erik Mericas

Peichun Peter Liu

A method of performing instructions in a computer processor architecture includes determining that a load instruction is being dispatched. Destination related data of the load instruction is written into a mapper of the architecture. A determination that a compare immediate instruction is being dispatched is made. A determination that a branch conditional instruction is being dispatched is made. The branch conditional instruction is configured to wait until the load instruction produces a result before the branch conditional instruction issues and executes. The branch conditional instruction skips waiting for a finish of the compare immediate instruction.

Dependency skipping in a load-compare-jump sequence of instructions by incorporating compare functionality into the jump instruction and auto-finishing the compare instruction

A system, processor, programming product and/or method including: an instruction dispatch unit configured to dispatch instructions of a compare immediate-conditional branch instruction sequence; and a compare register having at least one entry to hold information in a plurality of fields. Operations include: writing information from a first instruction of the compare immediate-conditional branch instruction sequence into one or more of the plurality of fields in an entry in the compare register; writing an immediate field and the ITAG of a compare immediate instruction into the entry in the compare register; writing, in response to dispatching a conditional branch instruction, an inferred compare result value into the entry in the compare register; comparing a computed compare result value to the inferred compare result value stored in the entry in the compare register; and not execute the compare immediate instruction or the conditional branch instruction.

Inferring future value for speculative branch resolution in a microprocessor

Aspects of the invention include includes determining a first instruction in a processing pipeline, wherein the first instruction includes a compare instruction, determining a second instruction in the processing pipeline, wherein the second instruction includes a conditional branch instruction relying on the compare instruction, determining a predicted result of the compare instruction, and completing the conditional branch instruction using the predicted result prior to executing the compare instruction.

Inferring future value for speculative branch resolution

A computer processor includes a dispatch stage and a dependency skipping execution unit. The dispatch stage is configured to dispatch a plurality of instructions that include a general purpose instruction configured to produce first data, a dependent instruction configured to produce second data, and an indirect dependent instruction configured to produce third data. The dependency skipping execution unit is configured to monitor the plurality of instructions and to process the indirect dependent instruction in response to the general purpose instruction producing the first data. The indirect dependent instruction is issued independently from the second data produced by the indirect dependent instruction.

Dependency skipping execution

Embodiments for implementing a fused multiply-multiply-accumulate ('FMMA') unit by one or more processors in a computing system. Mantissas for two products, an exponent difference of the two products serving as an alignment shift amount for a product of the two products having a smallest exponent, and an alignment shift amount for an addend relative to an alternative product of the two product having a larger exponent may be determined in parallel. The addend may be aligned relative to the alternative product having the larger exponent. The product having the smallest exponent may be aligned relative to the alternative product having the larger exponent according to the alignment shift amount.

Ultra-low precision floating-point fused multiply-accumulate unit

Embodiments of the present invention include methods, systems, and computer program products for implementing instruction fusion after register rename. A computer-implemented method includes receiving, by a processor, a plurality of instructions at an instruction pipeline. The processor can further performing a register rename within the instruction pipeline in response to the received plurality of instructions. The processor can further determine that two or more of the plurality of instructions can be fused after the register rename. The processor can further fuse the two or more instructions that can be fused based on the determination to create one or more fused instructions. The processor can further perform an execution stage within the instruction pipeline to execute the plurality of instructions, including the one or more fused instructions.

Instruction fusion after register rename

Various embodiments are provided for providing a dynamic random-access memory ('DRAM') cache as second type memory in a computing system by a processor. A selected amount of bytes in a memory line may be cleared using one or more spare bits of the DRAM, a data compression operation, or a combination thereof. A cache directory and data may be stored in the memory line. The DRAM cache is configured as a cache of a second type memory.

Providing a dynamic random-access memory cache as second type memory

Aspects of the invention include detecting that all instructions in a first group of in-flight instructions have a status of finished. The first group of in-flight instructions is associated with a first allocated entry in a global completion table (GCT) which tracks a dispatch order and status of groups of in-flight instructions. The GCT includes a plurality of allocated entries including the first allocated entry and a second allocated entry. A second group of in-flight instructions dispatched immediately prior to the first group is associated with the second allocated entry in the GCT. Based at least in part on the detecting, the first allocated entry is merged into the second allocated entry to create a single merged second allocated entry in the GCT that includes completion information for both the first group of in-flight instructions and the second group of in-flight instructions. The first allocated entry is then deallocated.

Coalescing global completion table entries in an out-of-order processor

Technical solutions are described for a load-store unit (LSU) that executes a plurality of instructions in an out-of-order (OoO) window using multiple LSU pipes. The execution includes selecting an instruction from the OoO window, the instruction using an effective address; and if the instruction is a load instruction: and if the processing unit is operating in single thread mode, creating an entry in a first partition of a load reorder queue (LRQ) if the instruction is issued on a first load pipe, and creating the entry in a second partition of the LRQ if the instruction is issued on a second load pipe. Further, if the processing unit is operating in a multi-thread mode, creating the entry in a first predetermined portion of the first partition of the LRQ if the instruction is issued on the first load pipe and by a first thread of the processing unit.

Load-store unit with partitioned reorder queues with single cam port

Aspects of the invention include receiving, by a processor, a plurality of instructions at an instruction pipeline. The processor can further determine an operand bit field size for each of the received plurality of instructions. The processor can further compare the operand bit field size of at least a subset of the received instructions to a predetermined threshold. The processor can further fuse at least two of the received instructions that have an operand bit field size that meets the predetermined threshold. The processor can further perform an execution stage within the instruction pipeline to execute the received instructions, including the fused instructions.

Dynamic fusion based on operand size

Technical solutions are described for hazard detection of out-of-order execution of load and store instructions without using real addresses in a processing unit. An example includes an out-of-order load-store unit (LSU) for transferring data between memory and registers. The LSU detects a store-hit-load (SHL) in an out-of-order execution of instructions based only on effective addresses by: determining an effective address associated with a store instruction; determining whether a load instruction entry using said effective address is present in a load reorder queue; and indicating that a SHL has been detected based at least in part on determining that load instruction entry using said effective address is present in the load reorder queue. The LSU, in response to detecting the SHL, flushes instructions starting from a load instruction corresponding to the load instruction entry.

Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses

Technical solutions are described for issuing, by a load-store unit (LSU), a plurality of instructions from an out-of-order (OoO) window. The issuing includes, in response to determining a first effective address being used by a first instruction, the first effective address corresponding to a first real address, creating an effective real table (ERT) entry in an ERT, the ERT entry mapping the first effective address to the first real address. Further, the execution includes in response to determining an effective address synonym used by a second instruction, the effective address synonym being a second effective address that is also corresponding to said first real address: creating a synonym detection table (SDT) entry in an SDT, wherein the SDT entry maps the second effective address to the ERT entry, and relaunching the second instruction by replacing the second effective address in the second instruction with the first effective address.

Handling effective address synonyms in a load-store unit that operates without address translation

Aspects of the invention include tracking relative ages of instructions in a first-in-first-out (FIFO) issue queue of an out-of-order (OoO) processor. The FIFO issue queue is configured to add instructions to the issue queue in a sequential order and to remove instructions from the issue queue in any order including a non-sequential order. The tracking of relative ages of instructions includes maintaining a head pointer to a location of an oldest instruction in the issue queue and a tail pointer to a location of a last instruction added to the issue queue. It is determined periodically whether the tail pointer is pointing to a location that includes a valid instruction. The tail pointer is updated to point to a previous sequential location in the issue queue based at least in part on determining that the tail pointer is not pointing to a location that corresponds to a valid instruction.

Head and tail pointer manipulation in a first-in-first-out issue queue

Aspects of the invention include tracking dependencies between instructions in an issue queue. The tracking includes, for each instruction in the issue queue, identifying whether the instruction is dependent on each of a threshold number of instructions added to the issue queue prior to the instruction. The tracking also includes identifying whether the instruction is dependent on one or more other instructions in a group of instructions in the issue queue that were added to the issue queue prior to the instruction and that are not included in the threshold number of instructions that are tracked individually. A dependency between the instruction and the one or more other instructions in the group of instructions is tracked using a single summary bit that is set to indicate that a dependency exists between the instruction and the group of instructions. Instructions are issued from the issue queue based at least in part on the tracking.

Scalable dependency matrix with a single summary bit in an out-of-order processor

Growing community of inventors

Poughkeepsie, NY, United States of America

Balaram Sinharoy