Arm Limited

Balaji Venu

Xabier Iturbe

Mbou Eyole

Emre Özer

Giacomo Gabrielli

Emre Ozer

Reiley Jeyapaul

Antony John Penton

Matthias Lothar Boettcher

Matthew James Walker

Shidhartha Das

Milosch Meriac

Metin Gokhan Ünal

John Wakefield Brothers

Wei Wang

Matthew James Horsnell

François Christopher Jacques Botman

Damian Piotr Modrzyk

Kauser Yakub Johar

Jacob Eapen

David Michael Gilday

Rune Holm

Marco Bonino

There is provided a data processing apparatus and method. The data processing apparatus comprises a plurality of processing elements connected via a network arranged on a single chip to form a spatial architecture. Each processing element comprising processing circuitry to perform processing operations and memory control circuitry to perform data transfer operations and to issue data transfer requests for requested data to the network. The memory control circuitry is configured to monitor the network to retrieve the requested data from the network. Each processing element is further provided with local storage circuitry comprising a plurality of local storage sectors to store data associated with the processing operations, and auxiliary memory control circuitry to monitor the network to detect stalled data (S). The auxiliary memory control circuitry is configured to transfer the stalled data from the network to an auxiliary storage buffer (S) dynamically selected from amongst the plurality of local storage sectors (S).

Data processing apparatus and method for handling stalled data

A processor, method, and non-transitory computer-readable storage medium for performing a block matching between first data and second data are provided. The block matching is performed using an iterative process, wherein, for each iteration, a portion of the first data and a corresponding portion of the second data is selected using a sliding window approach. When differences data, used for block matching, is calculated for a specific subset of first and second data, many of the calculations overlap with those needed for a nearby subset. Summed area table, SAT, data used for determining the difference data is continuously stored and updated in a buffer, such that overlapping computations can be avoided.

Block matching between first data and second data

Provided is a data stream processor comprising a streamed data transceiver interface, a structure of processing units configurable to transform data received from a data source over the streamed data transceiver interface according to a specified output requirement, and a configuration unit operable in electronic communication with a data consumer to receive an output requirement and to configure the operation and linkage of a processing unit in the structure of processing units to transform input data to output data according to the specified output requirement; wherein the structure of processing units is further operable to provide the output data for output over the streamed data transceiver interface.

Data stream processor

A masked-vector-comparison instruction specifies a source vector operand comprising a plurality of source data elements, a mask value, and a comparison target operand. In response to the masked-vector-comparison instruction, an instruction decodercontrols processing circuitryto: for each active source data element of the source vector operand, determine whether the active source data element satisfies a comparison condition, based on a masked comparison between one or more compared bits of the active source data element and one or more compared bits of the comparison target operand, the mask value specifying a pattern of compared bits and non-compared bits within the comparison target operand and the active source data element; and generate a result value indicative of which of the source data elements of the source vector operand, if any, is an active source data element satisfying the comparison condition. This instruction is useful for variable length decoding operations.

Masked-vector-comparison instruction

Circuitry comprises processing circuitry configured to execute program instructions in dependence upon respective trigger conditions matching a current trigger state and to set a next trigger state in response to program instruction execution; the processing circuitry comprising: instruction storage configured to selectively provide a group of two or more program instructions for execution in parallel; and trigger circuitry responsive to the generation of a trigger state by execution of program instructions and to a trigger condition associated with a given group of program instructions, to control the instruction storage to provide program instructions of the given group of program instructions for execution.

Circuitry and method for instruction execution in dependence upon trigger conditions

One or more triggered-instruction processing elements are provided, a given triggered-instruction processing element comprising execution circuitry to execute processing operations in response to instructions according to a triggered instruction architecture. Input channel processing circuitry receives a given tagged data item (comprising a data value and a tag value) for a given input channel, and in response controls enqueuing of the data value of the given tagged data item to a selected buffer structure selected from among at least two buffer structures mapped onto register storage accessible to one or more of the triggered-instruction processing elements in response to a computation instruction for controlling performance of a computation operation. The selected buffer structure is selected based at least on the tag value, so data values of tagged data items specifying different tag values for the given input channel are allocatable to different buffer structures.

Input channel processing for triggered-instruction processing element

An apparatus, method and computer program, the apparatus comprising processing circuitry to execute instructions, issue circuitry to issue the instructions for execution by the processing circuitry, and candidate instruction storage circuitry to store a plurality of condition-dependent instructions, each specifying at least one condition. The issue circuitry is configured to issue a given condition-dependent instruction in response to a determination or a prediction of the at least one condition specified by the given condition-dependent instruction being met, and when the given condition-dependent instruction is a sequence-start instruction, the issue circuitry is responsive to the determination or prediction to issue a sequence of instructions comprising the sequence-start instruction and at least one subsequent instruction.

Issuing a sequence of instructions including a condition-dependent instruction

There is provided an apparatus, method and medium for data processing. The apparatus comprises a register file comprising a plurality of data registers, and frontend circuitry responsive to an issued instruction, to control processing circuitry to perform a processing operation to process an input data item to generate an output data item. The processing circuitry is responsive to a first encoding of the issued instruction specifying a data register, to read the input data item from the data register, and/or write the output data item to the data register. The processing circuitry is responsive to a second encoding of the issued instruction specifying a buffer-region of the register file for storing a queue of data items, to perform the processing operation and to perform a dequeue operation to dequeue the input data item from the queue, and/or perform an enqueue operation to enqueue the output data item to the queue.

Processing of issued instructions

An apparatus comprises a plurality of redundant processing units to perform data processing redundantly in lockstep; common mode fault detection circuitry to detect an event indicative of a potential common mode fault affecting each of the plurality of redundant processing units; a memory shared between the plurality of redundant processing units; and memory checking circuitry to perform a memory scanning operation to scan at least part of the memory for errors; in which the memory checking circuitry performs the memory scanning operation in response to a common mode fault signal generated by the common mode fault detection circuitry indicating that the event indicative of a potential common mode fault has been detected.

Memory scanning operation in response to common mode fault signal

An apparatus has a processing pipeline () comprising an execute stage () and at least one front end stage (), (), () for controlling which micro operations are issued to the execute stage. The pipeline has an intra-core lockstep mode of operation in which the at least one front end stage (), (), () issues micro operations for controlling the execute stage () to perform main processing and checker processing. The checker processing comprises redundant operations corresponding to associated main operations of at least part of the main processing. Error handling circuitry (), () is responsive to the detection of a mismatch between information associated with given checker and main operations to trigger a recovery operation to correct an error and continue forward progress of the main processing.

Error recovery for intra-core lockstep mode

Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, to determine indicators of potential errors in a multi-processing core lockstep computing device comprising a plurality of processing cores, based, at least in part, on observations of output signals generated by at least two processing cores of the plurality of processing cores. A built-in self-test (BIST) procedure may then be based, at least in part, on the determining indicators.

Device, system and process for redundant processor error detection

A buffer (), (), (), (), (), (), (-) has a number of entries for buffering items associated with data processing operations. Buffer control circuitry () has a redundant allocation mode in which, on allocating a given item to the buffer, the item is allocated to two or more redundant entries of the buffer. On reading or draining an item from the buffer, the redundant entries are compared and an error handling response is triggered if a mismatch is detected. By effectively reducing the buffer capacity, this simplifies testing for faults in buffer entries.

Handling errors in buffers

An apparatus is provided to measure vulnerability of a circuit to transient errors. The circuit includes processing circuitry and a plurality of flops. The apparatus includes categorisation obtaining circuitry that obtains a vulnerability categorisation of the flops. The vulnerability categorisation indicates whether each flop is vulnerable, conditionally vulnerable, or isolated. Analysis circuitry determines, for at least one cycle of the processing circuitry, a set of the flops that are currently vulnerable, based on the vulnerability categorisation of the flops.

Stabilised failure estimate in circuits

Aspects of the present disclosure relate to an apparatus comprising processing circuitry to execute a plurality of code sequences, and configuration storage to store mode control data for the processing circuitry. When the processing circuitry is executing one of said plurality of code sequences, the mode control data is set so as to identify a high resilience mode of operation of the processing circuitry where usage of one or more components of the processing circuitry is modified so as to increase resilience of the processing circuitry to faults relative to a default mode of operation of the processing circuitry.

Apparatus and method for increasing resilience to faults

Examples of the present disclosure relate to a method for anomaly response in a system on chip. The method comprises measuring a magnitude of a transient anomaly event in an operating condition of the system on chip. Based on the magnitude it is determined, for each of a plurality of components of the system on chip, an indication of susceptibility of that component to an anomaly event of the measured magnitude. Based on the determined indications of susceptibility for each of the plurality of components, an anomaly response action is determined. The method then comprises performing the anomaly response action.

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Cambridge, United Kingdom

Balaji Venu