Intel Corporation

Mcafee, Inc.

Graphcore Limited

Balaji Vembu

Altug Koker

Joydeep Ray

Abhishek R Appu

Prasoonkumar Surti

Kamal Sinha

Murali Ramadoss

Vasanth Ranganathan

Eriko Nurvitadhi

Subramaniam M Maiyuran

Nicolas C Galoppo Von Borries

Rajkishore Barik

Tsung-Han Lin

Sanjeev S Jahagirdar

Travis T Schluessler

Kiran Chand Veernapu

Elmoustapha Ould-Ahmed-Vall

David M Puffer

Sara S Baghsorkhi

Jeffery S Boles

Nikos Kaburlasos

Narayan Srinivasa

Ankur N Shah

Feng Chen

Dukhwan Kim

Justin E Gottschlich

Linda L Hurd

Wenyin Fu

Josh B Mastronarde

Anbang Yao

Xiaoming Chen

John H Feit

Nadathur Rajagopalan Satish

Pattabhiraman K

Ben J Ashbaugh

Aditya Navale

Guei-Yuan Lueh

Jacek Kwiatkowski

Devan Burke

Adam T Lake

James A Valerio

Michael Apodaca

Chandrasekaran Sakthivel

Karthik Vaidyanathan

John Charles Weast

Tatiana Shpeisman

Ping Tak Tang

Michael S Strickland

Gabor Liktor

Jonathan Kennedy

Kun Tian

Peter L Doyle

Liwei Ma

Hugues Labbe

Niranjan L Cooray

Mike B Macpherson

Sanu K Mathew

Kai Xiao

Eric C Samson

Mark A Anders

Himanshu Kaul

David M Durham

Prashant Dewan

Scott R Janus

Tomer Bar-On

Lakshminarayanan Striramassarma

Daniel Nemiroff

Rajesh M Sankaran

Zhi Hu Wang

Atsuo Kuwahara

Ingo Wald

Abhishek Venkatesh

Arvind A Kumar

Changliang Wang

Deepak Shashidhar Vembar

Mahesh S Natu

Daniel John Pelham Wilkinson

Gilbert A Neiger

Siddhartha Chhabra

Uday R Savagaonkar

David I Poisner

Richard A Uhlig

Ioannis T Schoinas

Aravindh V Anantaraman

Zhi Jun Wang

Jason Martin

Ravi L Sahita

Vedvyas Shanbhogue

Carlos V Rozas

Tomas G Akenine-Moller

Francis X Mckeen

Vincent R Scarlata

Geoffrey S Strongin

Karanvir S Grewal

Jason Daniel Tanner

Nitin V Sarangdhar

Zohar Bogin

Gary L Graunke

Mike MacPherson

Michael Mishaeli

A mechanism is described for detecting, at training time, information related to one or more tasks to be performed by the one or more processors according to a training dataset for a neural network, analyzing the information to determine one or more portions of hardware of a processor of the one or more processors that is configurable to support the one or more tasks, configuring the hardware to pre-select the one or more portions to perform the one or more tasks, while other portions of the hardware remain available for other tasks, and monitoring utilization of the hardware via a hardware unit of the graphics processor and, via a scheduler of the graphics processor, adjusting allocation of the one or more tasks to the one or more portions of the hardware based on the utilization.

Coordination and increased utilization of graphics processors during inference

In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.

Regional adjustment of render rate

One embodiment provides for a compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including a multi-bit input value and a one-bit weight associated with a neural network, as well as an arithmetic logic unit including a multiplier, an adder, and an accumulator register. To execute the decoded instruction, the multiplier is to perform a fused operation including an exclusive not OR (XNOR) operation and a population count operation. The adder is configured to add the intermediate product to a value stored in the accumulator register and update the value stored in the accumulator register.

Compute optimizations for neural networks

In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

Engine to enable high speed context switching via on-die storage

In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

Dynamic precision for neural network compute operations

An apparatus and method are described for managing data which is biased towards a processor or a GPU. For example, an apparatus comprises a processor comprising one or more cores, one or more cache levels, and cache coherence controllers to maintain coherent data in the one or more cache levels; a graphics processing unit (GPU) to execute graphics instructions and process graphics data, wherein the GPU and processor cores are to share a virtual address space for accessing a system memory; a GPU memory addressable through the virtual address space shared by the processor cores and GPU; and bias management circuitry to store an indication for whether the data has a processor bias or a GPU bias, wherein if the data has a GPU bias, the data is to be accessed by the GPU without necessarily accessing the processor's cache coherence controllers.

Apparatus and method for managing data bias in a graphics processing architecture

One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute an intermediate product of 16-bit operands and to compute a 32-bit sum based on the intermediate product.

Instructions and logic to perform floating point and integer operations for machine learning

A mechanism is described for facilitating intelligent thread scheduling at autonomous machines. A method of embodiments, as described herein, includes detecting dependency information relating to a plurality of threads corresponding to a plurality of workloads associated with tasks relating to a processor including a graphics processor. The method may further include generating a tree of thread groups based on the dependency information, where each thread group includes multiple threads, and scheduling one or more of the thread groups associated a similar dependency to avoid dependency conflicts.

Efficient thread group scheduling

In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive an input from one or more detectors proximate a display to present an output from a graphics pipeline, determine that a user is not interacting with the display, and in response to a determination that the user is not interacting with the display, to reduce a frame rendering rate of the graphics pipeline. Other embodiments are also disclosed and claimed.

Reduce power by frame skipping

Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

Compute optimization mechanism for deep neural networks

Embodiments described herein provide techniques to facilitate scalable interrupts and workload submission for a virtualized graphics processor. The techniques include memory-based interrupt reporting and shared work queue submission for multiple software domains.

Scalable I/O virtualization interrupt and scheduling

One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product.

Techniques to improve performance of matrix multiply operations are described in which a compute kernel can specify one or more element-wise operations to perform on output of the compute kernel before the output is transferred to higher levels of a processor memory hierarchy.

Machine learning sparse computation mechanism

A system and method for encrypting and decrypting data exchanged between a multi-tile processing unit and a storage, where a plurality of keys are used for the encryption. Each of the plurality of keys is associated with a different one or more sets of the processors. Encryption hardware is configured to select a key to use for encryption/decryption operations in dependence upon the set of tiles associated with the data being exchanged. Each write request from a tile contains identifier bits associated with that tile's set of tiles, enabling the encryption hardware to select the key to use for encrypting the data in the write request. Each read completion for a tile contains identifier bits associated with that tile's set of tiles, enabling the encryption hardware to select the key to use for decrypting the data in the read completion.

Multiple key management

One embodiment provides a graphics processor comprising a system interface and circuitry coupled with the system interface. The circuitry includes an execution resource and a preemption status register. The execution resource is configured to execute an instruction. During execution of the instruction, the execution resource is to receive a request to preempt execution of a thread associated with the instruction and, based on a value stored in the preemption status register, execute at least one additional instruction after receipt of the request to preempt execution of the thread.

Page faulting and selective preemption

Growing community of inventors

Folsom, CA, United States of America

Balaji Vembu