International Business Machines Corporation

Balaji Upputuri

Raghu G GopalaKrishnaSetty

Kshitij Kulshreshtha

Raghu Gaurav GopalaKrishnaSetty

Ravi Lakshmipathy

Thamaraiselvan Subramani

A method for creating an architecture to support Q-gating for launch-off-shift (LOS) scan testing using a plurality of flip-flops is provided. The method may include applying a common clock signal to each clock input of the plurality of flip-flops and applying a gated scan enable signal to each scan enable input of the plurality of flip-flops. The method may further include applying a global scan enable signal directly to each of a plurality of Q-gates corresponding to each of the plurality of flip-flops, wherein the global scan enable signal traverses a signal path that bypasses combinational logic located between any two flip-flops of the plurality of flip-flops.

Q-gating cell architecture to satiate the launch-off-shift (LOS) testing and an algorithm to identify best Q-gating candidates

According to at least one exemplary embodiment, a synchronous active high reset scan flip flop is provided. The synchronous active high reset scan flip flop may include a data input, a serial input, a test enable input, a reset input, a clock input, a device output. It may also include an AND gate configured to receive the serial input and the test enable input and a multiplexer configured to receive the data input and a first output signal received from the AND gate. The multiplexer is operable in response to the reset input which is used to reset the flip flop in function mode, and permit scan test in test mode. The synchronous active high reset scan flip flop may also include a storage element configured to receive a second output signal received from the multiplexer and operable in response to a clock signal received from the clock input.

Optimized synchronous scan flip flop circuit

A processor-implemented method for selective Q-gating flip-flops in a plurality of flip-flops contained in a design is provided. The method may include determining a maximum width, a maximum depth, and a maximum congestion value in the design and determining a relative width, a relative depth, and a relative congestion value for each of the plurality of flip-flops in the design. The method may further include determining grade values for each of the plurality of flip-flops in the design based on a ratio between the relative width, the relative depth and the relative congestion value, and the maximum width, the maximum depth, and the maximum congestion value, respectively and determining an overall summed value for each of the plurality of flip-flops. Then the method may sort the plurality of flip-flops based on the overall summed value for the plurality of flip-flops according to magnitude.

Algorithm to identify best Q-gating candidates and a Q-gating cell architecture to satiate the launch-off-shift (LOS) testing

Aspects of the invention provide for a method of delay defect testing in integrated circuits. In one embodiment, the method includes: generating at least one test pattern based on a transition fault model type; evaluating a dynamic voltage drop for the at least one pattern during a capture cycle and generating a voltage drop value for the at least one test pattern; performing a static timing analysis, using the voltage drop value for the at least one test pattern; evaluating a plurality of paths in the at least one pattern; and masking each path that fails to meet a timing requirement.

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Bengaluru, India

Balaji Upputuri