Samsung Electronics Co., Ltd.

Balaji Somu Kandaswamy

Tushar Vrind

Venkata Raju Indukuri

Raju Udava

Raju Udava Siddappa

Chandan Kumar

Anirban Saha

Patana Bhagwan Reddy

Venakata Raju Indukuri

A code coverage method for an embedded System on Chip (SoC) includes detecting a presence of a utility function in target source code; adding a hook function to the target source code; and recording at least one property of the utility function based on the hook function in a bit array in a memory of the SoC. The method may further include extracting at least one recorded property from bit arrays in the memory; and generating a code coverage report based on an analysis of the extracted properties.

Code coverage method for embedded system on chip

Various example embodiments herein provide a computerized method for scheduling a plurality of tasks for an operating system on a multicore processor. The method includes identifying the plurality of tasks to be executed on the multicore processor and determining a task schedule for scheduling of the plurality of tasks by providing a higher preference to the CPU-bound task than the non CPU-bound task. Further, the method includes scheduling the plurality of tasks on the multicore processor based on the task schedule.

Method, system, apparatus, and/or non-transitory computer readable medium for the scheduling of a plurality of operating system tasks on a multicore processor and/or multi-processor system

The various embodiments of the present invention disclose a method for reducing interrupt latency in embedded systems. According to at least one example embodiment of the inventive concepts, the method for reducing interrupt latency in embedded systems, the method comprises steps of toggling, by a processor, from a supervisor (SVC) mode to an interrupt request (IRQ) mode on receiving an interrupt, identifying, by the processor, a Task Control Block (TCB) of a preempted task on receiving the interrupt, enabling, by the processor, the IRQ stack as a pseudo preempted task context table, and storing the preempted task context information in the IRQ stack, wherein a register set is stored in IRQ stack before processing the received interrupt.

Method for reducing interrupt latency in embedded systems

A method and system for providing memory management in a Real-Time Operating System (RTOS) based system are provided. The method includes creating a plurality of tasks with a two level stack scheme comprising a first level stack and a second level stack, scheduling a first task for execution by moving a stack pointer from the first level stack to the second level stack, determining whether the first task is pre-empted, allocating the second level stack to the first task in a second state if the first task is not pre-empted, changing an active task for execution, determining whether the first task relinquishes control from the second state and is waiting for a resource, moving the stack pointer back from the second level stack to the first level stack if the first task relinquishes itself and providing the second level stack for use by a second task.

Method and system for providing stack memory management in real-time operating systems

Method and apparatuses are provided for providing preemptive task scheduling for a Real Time Operating System (RTOS). A two-level priority is assigned to each task that is created. The two-level priority includes a kernel priority and a user-defined priority. A priority bitmap corresponding to the kernel priority is created. A priority bit in the priority bitmap is enabled. The priority bit indicates a status of a respective task.

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Bengaluru, India

Balaji Somu Kandaswamy