Globalfoundries Inc.

Globalfoundries U.S. Inc.

Globalfoundries U.S. 2 LLC

Balaji Jayaraman

Ramesh Raghavan

Toshiaki Kirihata

Rajesh Reddy Tummuru

Thejas Kempanna

Janakiraman Viraraghavan

Krishnan Santhana Rengarajan

Chandrahasa Reddy Dinnipati

Amit K Mishra

Edward J Nowak

Kota V R M Murali

Ninad D Sathaye

Rajesh Sathiyanarayanan

Jay M Shah

Navin Agarwal

Ming Yin

Aditya S Auyisetty

The present disclosure relates to integrated circuits, and more particularly, to a wordline system architecture supporting an erase operation and current-voltage (I-V) characterization and methods of manufacture and operation. In particular, the present disclosure relates to a structure including: a twin cell circuit which is connected to a wordline of a memory array; a sourceline driver which is connected to a sourceline of the memory array for providing a cell level current-voltage (I-V) access of the twin cell circuit; and an integrated analog multiplexor which is connected to the twin cell circuit.

Wordline system architecture supporting erase operation and I-V characterization

Embodiments of the present disclosure provide an apparatus including: a sense amplifier coupled to a memory array and having a set of output terminals, a latch coupled to a first output terminal of the sense amplifier, and a comparator coupled to the latch and a second output terminal of the sense amplifier.

Apparatus and related method to indicate stability and instability in bit cell

The present disclosure relates to integrated circuits, and more particularly, to a method for identifying unprogrammed bits for one-time-programmable memory (OTPM) and a corresponding structure. In particular, the present disclosure relates to a structure including: a read circuit configured to perform at least one read operation at an address for a twin-cell one-time-programmable-memory (OTPM); and a comparison circuit configured to identify whether at least one bit of the address for the twin-cell OTPM has been programmed based on the at least one read operation.

Structures and methods of identifying unprogrammed bits for one-time-programmable-memory (OTPM)

A Physically Unclonable Function (PUF) structure includes an array of twin cells divided into two portions: one with first columns and one with second columns. Cells in each first column are connected to a corresponding pair of first bitlines. Cells in each second column are connected to a corresponding pair of second bitlines. A first column decoder is connected to the first bitlines and to a first input of sense amplifier (SA) and a second column decoder is connected to the second bitlines and to a second input of SA. Each read operation to generate a bit is directed to a first cell in a first column and a second cell in a second column and, during the read operation, signals on only one first bitline of the first column containing the first cell and only one second bitline of the second column containing the second cell are compared.

Twin cell memory-based physically unclonable function

The present disclosure relates to a data dependent sense amplifier with symmetric margining. In particular, the present disclosure relates to a structure including a bias generator circuit that is configured to provide symmetric margining between two logic states of a memory circuit.

Data dependent sense amplifier with symmetric margining

Aspects of the present disclosure include methods and test structures for an intermediate metal level of an integrated circuit (IC). A method according to the present disclosure can include: fabricating a first plurality of metal levels including an intermediate metal level of an IC structure, the intermediate metal level being one of a plurality of metal levels in the IC structure other than a capping metal level of the IC structure; performing a first functional test on a first circuit positioned within the intermediate metal level; fabricating a second plurality of metal levels after performing the first functional test, the second plurality of metal levels including the capping metal level of the IC structure; and performing a second functional test on a second circuit positioned within the plurality of metal levels, after the fabricating of the capping metal level.

Test method and structure for integrated circuits before complete metalization

A multi-time programmable memory (MTPM) memory cell and method of operating. Each MTPM bit cell including a first FET transistor and a second FET transistor having a first common connection, and said second FET transistor and a third FET transistor having a second common connection, said first and second connected FET transistors programmable to store a first bit value, and said second FET and said third connected FET transistors programmable to store a second bit value, wherein said first FET transistor exhibits a low threshold voltage value (LVT), said second FET transistor exhibits an elevated threshold voltage value HVT and said third FET transistor exhibits a threshold value LVT lower than HVT. The MTPM cell enables two bits of information to be stored as default bit values like an electrical fuse. To store opposite bit values, the LVT transistors are programmed such that their threshold voltage is higher than that of HVT.

Dual-bit 3-T high density MTPROM array

A Multi-Time-Programmable-Memory (MTPM) array architecture, whose structure comprising of having Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) memory elements arranged in a set of twin-pairs coupled by wordlines (WLs), bitlines (BLs) and sourcelines (SLs). More specifically, the use of inactive portions of the MTPM array structure as substitutes for conventional BL write driver areas by utilizing a set of twin-pairs acting in parallel. These substituted twin-pair sets will improve programming efficiency (VGS) and retention (VDS) through a lowering Interconnect (IR) drop and VDS drops at the BL write driver.

Distributed current source/sink using inactive memory elements

Approaches for a memory including a cell array are provided. The memory includes a first device of the cell array which is connected to a bitline and a node and controlled by a word line, and a second device of the cell array which comprises a third device which is connected to a source line and the node and controlled by the word line and a fourth device which is connected between the word line and the node. In the memory, in response to another word line in the cell array being activated and the word line not being activated to keep the first device in an unprogrammed state, the third device isolates and floats the node such that a voltage level of a gate to source of the first device is clamped down by the fourth device to a voltage level around zero volts.

Disturb free bitcell and array

A system and method of operating a twin-transistor single bit multi-time programmable memory cell to provide a high gain, sensing scheme for small signals. The memory cell includes a pair of a first transistor and a second transistor providing a differential signal output. The first transistor of the memory cell couples a first circuit leg having a first current source load transistor and the second transistor couples a second circuit leg having a second current source load transistor. A programmed value is represented by a voltage threshold shift in one of the first or second transistors. A feedback circuit receives one of: a first signal or a second signal of the differential signals, and generates, in response, a feedback signal which is simultaneously applied to bias each current source load transistor in each the first and second circuit legs to amplify a voltage differential between the differential signal outputs.

Data-dependent self-biased differential sense amplifier

A workfunction modulation-based sensor comprising a field-effect transistor (FET). The FET comprises a substrate, a gate dielectric, a metal gate, a source, a drain, and a layer of sensing material that is electrically connected to the metal gate. An electrical connection that connects to the source of the FET. An electrical connection that connects to the drain of the FET. An electrical connection that connects to the layer of sensing material. An environment that includes an adsorbate gas surrounding, at least a portion of, the layer of sensing material. Wherein the sensing material is adapted to adsorb, at least in part, the adsorbate gas. The amount of adsorbate gas adsorbed on the layer of sensing material modulates the workfunction of the FET such that the degree of adsorbate gas adsorption corresponds to one of the temperature or pressure associated with the environment of the FET.

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Bengaluru, India

Balaji Jayaraman