Intel Corporation

Bala Natarajan

Johanna M Swan

Valluri Ramana Rao

Chien Chiang

Greg Atwood

Mark T Bohr

Ravi V Mahajan

Raj Nair

A voltage regulation module and system for an integrated circuit die. The voltage regulation module includes an interposer situated in a stack between a substrate and the integrated circuit die. The interposer includes a hybrid array of voltage regulation elements for receiving voltage from the power supply and for down-converting the voltage from the power supply into a regulated voltage supplied to the integrated circuit die. The hybrid array of voltage regulation elements includes both high-bandwidth linear regulation elements for providing voltage regulation to areas on the integrated circuit die that intermittently demand relatively high current levels, and low-bandwidth switching regulator elements that are highly power efficient.

Silicon interposer-based hybrid voltage regulator system for VLSI devices

An electronic assembly is assembled by stacking two or more integrated circuit dies on top of one another. Prior to singulation, an opening is laser-drilled into an upper die, and subsequently filled with a conductive member. The conductive member is located on a lower die and interconnects integrated circuits of the upper and lower dies. Laser-drilling allows for faster throughput when compared to, for example, etching, especially if a small number of openings has to be formed. The opening is laser-drilled from an upper surface of the upper die all the way through the die, which allows for the use of alignment marks on an upper surface of the upper die.

Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme

The opening is initially fabricated in an upper surface of a wafer substrate, which allows for the use of alignment features on the upper surface of the wafer substrate. The openings are then filled with plugs. An integrated circuit is then manufactured over the upper surface of the substrate and the plugs. The plugs are located below the integrated circuit and do not take up 'real estate' reserved for metal layers of the integrated circuit. A carrier is then bonded to an upper surface of the integrated circuit, whereafter a lower portion of the wafer substrate is removed in a grinding and etching operation. The plugs are then removed through a lower surface of the wafer substrate, whereafter the openings are filled with conductive members in a plating operation. A metal redistribution layer can be formed on a lower surface of the wafer substrate, because the carrier provides sufficient rigidity.

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Phoenix, AZ, United States of America

Bala Natarajan