Intel Corporation

Bala K Iyer

Prashant Saxena

Charles Lockwood

Prashant S Sawkar

James R Wuerfel

Peter J Lopez

Nirmal Govind

Silvian Goldenberg

Embodiments of a method of optimally scheduling, in near real-time, workunits for processing on processing stations in a processing system, while accounting for constraints such as processing station qualifications by workunit type and service type, and to meet certain business objectives such as cycle time and demand targets, are described. A method of scheduling the processing of workunits in a processing system comprises defining a plurality of workunits, aggregating the work units by workunit type and service to be performed on each workunit to define one or more workunit type-service type groupings. The method further allocates capacity of one or more processing stations to workunit type-service type groupings, assigns workunits of the plurality of workunits to meet the allocated capacity, and sequences the workunit type-service type groupings and workunits on each processing station of the one or more processing stations. Other embodiments are described and claimed.

Optimization-based process scheduling method and system

Provided are a method, system, and program for processing and verifying circuit designs. A circuit design specification written in a hardware definition language is received and zero delay black box code is added to the circuit design specification to position the zero delay black boxes at sequential elements. A synthesis of the circuit design specification is performed to generate a retimed implementation of the circuit design specification. The black boxes are processed in the retimed implementation to verify the synthesis of the circuit design.

Processing and verifying retimed sequential elements in a circuit design

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Hillsboro, OR, United States of America

Bala K Iyer