Cirrus Logic Inc.

Baker Scott, Iii

Edmund Mark Schneider

Adrian Maxim

Melvin L Hagge

Raghunath Krishna Rao

Jeffrey A Niehaus

Miroslav V Dokic

James S Divine

Zheng Luo

John Robert Pacourek

Terry Ritchie

A loop filter device and method for implementing a loop filter for a phase locked loop (&ldquo;PLL&rdquo;) circuit, which locks a frequency of a signal to a reference frequency, are disclosed. The loop filter includes a proportional path circuit and an integral path circuit. The proportional path circuit receives a charge pump output and determines and holds a charge to be directed to or taken from a PLL circuit throughout an update period based on a detected phase difference for the update period for locking a frequency of a signal for a PLL circuit to a reference frequency. The integral path circuit is coupled to the proportional path circuit, and the integral path circuit receives another charge pump output and tracks a total charge level for the PLL circuit based on phase differences for present and prior update periods.

Low-jitter loop filter for a phase-locked loop system

An audio decoder 100 for operating on a received compressed audio data stream compressed using an algorithm employing transform encoding and a bit allocation routine. A first processor 200 performs a first set of operations on the received compressed audio data stream including parsing the compressed audio data stream, recovering data fields within the compressed audio data stream, calculating a bit allocation, and passing frequency domain coefficients to shared memory. A second digital signal processor 100b performs a second set of operations on data passed from the first digital signal processor to shared memory including performing inverse transform operations on the data passed from the first digital signal processor.

Dual processor digital audio decoder with shared memory data transfer

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Boulder, CO, United States of America

Baker Scott, Iii