National Instruments Corporation

Synopsys, Inc.

Baijayanta Ray

Alexander Rabinovitch

Nikhil A Deshmukh

Abhay Samant

Pratik Prabhanjan Brahma

Manish Shroff

Sartaj Chaudhary

Utkarsh Gupta

Ankit Sethi

Venkataraghavan Punnapakkam Krishnan

Sriram Balasubramanian

Dalavaipatnam Rangarao Seetharaman

Kunal Agarwal

A method includes determining a plurality of signals that have been selected for waveform capture, forming, based on a respective numbers of clock cycles for the plurality of signals to update, a first group of signals and a second group of signals, sampling the first group of signals according to a first sampling clock signal to produce a first set of sampled signals, and sampling the second group of signals according to a second sampling clock signal to produce a second set of sampled signals. The method also includes generating a waveform capture frame based on the first set of sampled signals and the second set of sampled signals.

Waveform capture using multicycle path properties

Circuit designs are emulated to verify the functionality of the circuit design. Emulating the circuit design includes obtaining a circuit design. The circuit design includes clock signals. Each of the clock signals is a data path clock signal. Further, a first clock signal of the clock signals is determined to be faster than a second clock signal of the clock signals. Rising edges and falling edges of the second clock signal are aligned with rising edges of the first clock signal to generate a realigned clock signal based on determining that the first clock signal is faster than the second clock signal. The circuit design is emulated using the realigned clock signal.

Clock signal realignment for emulation of a circuit design

A system and method for emulation receives a circuit design driven by a primary clock signal. The circuit design includes reset circuitry and sequential circuitry connected to the reset circuitry. The circuit design includes a secondary clock signal that is slower than the primary clock signal. The reset circuitry generates a reset signal that is a function of the secondary clock signal. The secondary clock signal is remodeled at a transition edge of the primary clock signal, and a predicted reset signal is generated subsequent to the reset signal at the transition edge of the primary clock signal. An operation of the circuit design is emulated based on the predicted reset signal such that the predicted reset signal from the reset circuitry propagates through multiple cycles of the primary clock signal.

Multicycle path prediction of reset signals

Emulating a circuit design includes remodeling the clock signals of the circuit design. A circuit design includes clock signals that are based on a root clock signal. The clock signals are analyzed to identify a first clock signal of the clock signals that is faster than a second clock signal of the clock signals. The second clock signal is remodeled based on the first clock signal. An updated circuit design is generated based on remodeled second clock signal, and operation of the updated circuit design is emulated.

Transformations for multicycle path prediction of clock signals

A system, method and memory medium for performing blind equalization. A block {u} of the baseband samples is received. A function J of a vector f is minimized to determine a minimizer f. The function J depends on vector f according to J(f)=&#x3a3;(|y|&#x2212;&#x3b3;). The summation &#x3a3; corresponds to a sequence {y} of equalized samples. The sequence {y} of equalized samples is related to the block {u} according to a convolution relation {y}={u}*f. Parameter &#x3b3; is a current modulus value. The current modulus value &#x3b3; is updated to equal a ratio of a fourth moment of the sequence {y} to a second moment of the sequence {y}. The minimization and parameter update operations are repeated for a series of received blocks of baseband samples. The minimizer ffrom a last of the repetitions is used to determine final equalized samples.

Mechanism for performing equalization without prior knowledge of modulation type or constellation order

A system and method for performing frame and symbol timing synchronization on samples of a received signal that includes a series of frames. Each frame includes a known preamble and payload data. A start-of-frame time is estimated by scanning the received signal samples for the self similarity of two successive preambles. A carrier frequency offset (CFO) is estimated by maximizing a correlation between a magnitude spectrum of the received signal and a magnitude spectrum of a known preamble model. A fine estimate for the CFO is determined by computing a phase difference between samples separated by p repetitions of the base pattern for various values of index p, and computing a slope of a least squares affine fit to the phase differences. Additional operations are performed to find an optimal symbol starting point, to perform carrier phase synchronization and to detect the start of payload data.

Frame and symbol timing recovery for unbursted packetized transmissions using constant-amplitude continuous-phase frequency-modulation

Frame and carrier synchronization for unbursted packetized transmissions using constant-amplitude continuous-phase frequency-modulation

System and methods and memory media for identifying a rogue base station. A receiver captures an input signal that includes a mixture of the rogue station's transmission and the transmission of a victim base station. The victim station's transmission is removed from the mixture. A plurality of channel signals are extracted from the residual signal. The channel signals are analyzed which of them are 'valid', i.e., contain a GMSK-modulated GSM signal. The 'valid' channel signals are low pass filtered and then analyzed to determine which of them corresponds to the beacon channel. Information identifying the rogue base station is extracted from the beacon channel.

Identifying rogue GSM base stations by intercepting downlink beacon channels

Variable modulus mechanism for performing equalization without a priori knowledge of modulation type or constellation order

Systems and methods and memory media for performing modulation type detection. An attempt is made to estimate an underlying symbol rate of a received signal. The received signal is compensated for carrier frequency offset. Two candidates for symbol timing offset are estimated from the compensated signal. The compensated signal is downsampled using each offset candidate. A set of features is computed for each of the two downsampled signals. For each downsampled signal, the set of features is compared to a corresponding set of thresholds to obtain a corresponding set of comparison results. The two sets of comparison results are used to determine the modulation type of the received signal. A second method for estimating symbol rate may be performed if the modulation type is found to be FSK.

Blind carrier/timing recovery and detection of modulation scheme

A system and method for determining the modulation type and constellation order of an input signal given that the modulation type and constellation order are known to belong to set of possible types/orders. A computer operates on samples of the input signal to compute signal features. The computer classifies the modulation type and the constellation order by comparing each feature to one or more corresponding threshold values. The results of the comparisons are used to determine the modulation type and constellation order of the input signal from the set of possible types/orders. The classification may be performed based on a decision tree, each leaf node of the decision tree corresponding to a type/order combination, and each non-leaf node corresponding to one or more of the comparisons. The set of possible types/order may include PSK with a number of different constellation orders and QAM with a number of different constellation orders.

Detecting the modulation type and/or constellation order of a PSK/QAM-modulated signal

Embodiments of the present invention can provide circuits and systems for computing a discrete Fourier transform (DFT) or an inverse discrete Fourier transform (IDFT). An embodiment includes an input circuit, an intermediate circuit, an output circuit, and an accumulator circuit. The input circuit can receive a set of input values, and can use a first set of degenerate rotators to generate a first set of intermediate values. The intermediate circuit can receive the first set of intermediate values, and can use a set of CORDICs (coordinate rotation digital computers) to generate a second set of intermediate values. The output circuit can receive the second set of intermediate values, and can use a second set of degenerate rotators to generate a third set of intermediate values. The accumulator circuit can receive the third set of intermediate values, and can use a set of accumulators to generate a set of output values.

Digital architecture for DFT/IDFT hardware

A system and method for classifying an input signal suspected of being a wireless LAN signal. Bursts are isolated based on an analysis of an average power signal that is derived from the input signal. A correlation-based test is performed to determine if the input signal contains a Barker code typical of DSSS transmissions. Another correlation-based test is performed to determine of the input signal contains a long training sequence typical of OFDM transmissions. The results of the two tests are used to classify the input signal as being DSSS, OFDM or neither.

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Bengaluru, India

Baijayanta Ray