Samsung Electronics Co., Ltd.

Sungkyunkwan University

Bai-Sun Kong

Young-Hyun Jun

Joung-Yeal Kim

Min-Su Kim

Hoi-jin Lee

Su-Jin Park

Myung-Jin Lee

Hoijin Lee

Mu-kyeng Jung

Hyungdong Roh

Sunwoo Kwon

Nak-won Heo

Mooyeol Choi

Chang Ho An

Byung-Hwa Jung

Sung-Chan Kang

Jae-Whui Kim

An exemplary embodiment of the present disclosure relates to a rail-to-rail class-AB buffer amplifier using compact adaptive biasing, and the rail-to-rail class-AB buffer amplifier using compact adaptive biasing includes an input stage generating a differential current pair based on a voltage difference between a first input signal and a second input signal, an amplification stage outputting a driving signal based on the differential current pair, an output stage connected to the amplification stage and outputting an output signal, an auxiliary current source switch which is on/off based on the driving signal of the amplification stage, and a current mirroring unit generating bias current and outputting the generated bias current to the input stage when the auxiliary current source switch is on.

Rail-to-rail class-AB buffer amplifier with compact adaptive biasing

A delta-sigma modulator includes a loop filter, a quantizer configured to change an analog output signal into a digital signal, and a digital-to-analog converter configured to receive the digital signal and including a first capacitor and a second capacitor. In a first sampling period, the first capacitor is discharged, and at the same time, the second capacitor is charged with a reference voltage. In a second sampling period, the digital signal includes noise caused by a clock jitter, the first capacitor is charged with a reference voltage, and the second capacitor is discharged and generates a charge corresponding to the noise. In a next first sampling period, the first capacitor is discharged, and at the same time, the second capacitor generates a noise current corresponding to the noise using the charge and is charged with a reference voltage.

Delta sigma modulator for shaping noise and audio codec having the same

A scan flip-flop circuit includes an input unit and an output unit. The data output unit is configured to provide a data output terminal with a data output signal in response to a data input signal and a first control signal in a first operation mode, and the data output unit is configured to prohibit the data output terminal from being provided with a power supply voltage and a ground voltage applied to the scan flip-flop circuit in response to the data input signal and the first control signal in a second operation mode. The scan output unit is configured to provide a scan output terminal with a scan output signal in response to a scan input signal and a second control signal in the second operation mode.

Scan flip-flop circuits and scan test circuits including the same

A clock gated circuit includes a pulse generator and a pulse level shifter. The pulse generator is driven by a first power supply voltage and is configured to receive a clock signal to generate a pulse and an inverted pulse. The pulse level shifter is driven by a second power supply voltage higher than the first power supply voltage and is configured to receive the pulse and the inverted pulse and to convert a level of the pulse in response to an enable signal.

Clock gated circuit and digital system having the same

A scan flip-flop circuit includes an input unit and an output unit. The input unit selects one of a data input signal and a scan input signal depending on an operation mode and generates an intermediate signal based on the selected signal. The output unit generates an output signal based on the intermediate signal and selects one of a data output terminal and a scan output terminal depending on the operation mode to provide the output signal through the selected output terminal. A voltage level at the selected output terminal bidirectionally transitions between a first voltage level and a second voltage level. A voltage level at a non-selected output terminal unidirectionally transitions between the first voltage level and the second voltage level.

A CMOS charge pump with improved latch-up immunity is provided. The CMOS charge pump includes a blocking transistor that disconnects first and second boost nodes from a bulk node in response to a blocking control signal, such that a bulk voltage can be maintained at a predetermined level or higher. The CMOS charge pump in a power-up period first precharges the bulk voltage before the main pump performs a boosting operation and prevents a latch-up phenomenon.

CMOS charge pump with improved latch-up immunity

Disclosed herein is an apparatus for outputting complementary signals using bootstrapping technology. The apparatus for outputting complementary signals includes a precharaged logic block, one or more output nodes, and a bootstrapping circuit block. The precharged differential logic block generates a differential signal depending on an input signal. The one or more output nodes output the complementary signals depending on the differential signal. The bootstrapping circuit block is shared by the one or more output nodes, and amplifies the complementary signals.

Apparatus for outputting complementary signals using bootstrapping technology

Provided is a semiconductor device for performing charge pumping. The semiconductor device may include a first pumping unit, a second pumping unit, and a controller. The first pumping unit may be configured to output a boosted voltage via an output node by using a first input signal and the initial voltage, where the boosted voltage is greater than an initial voltage. The second pumping unit may be configured to output the boosted voltage via the output node by using a second input signal and the initial voltage. The controller may be configured to control the first and second pumping units. Each of the first and second pumping units may include an initialization unit, a boosting unit, and a transmission unit. The initialization unit may be configured to control a voltage of a boosting node to be equal to the initial voltage during an initialization operation. The boosting unit may be configured to boost the voltage of the boosting node based on the first and second input signals. Also, the transmission unit may be configured to control output of the boosted voltage.

Semiconductor device for charge pumping

A charge pump circuit includes initialization units, each of which initializes a boost node to an initialization voltage. Boosting units each boost the boost node to a higher voltage than the initialization voltage in response to an input voltage. First and second pump circuits each include a transfer unit for transferring a voltage of the boost node to an output node and sharing the output node. The transfer unit of the first pump circuit includes two transfer transistors that are switched in response to a voltage of a control node of the first pump circuit and the voltage of the boost node of the second pump circuit. The transfer unit of the second pump circuit includes two transfer transistors that are switched in response to a voltage of a control node of the second pump circuit and the voltage of the boost node of the first pump circuit.

Charge pump circuit

A flip-flop circuit includes a precharging circuit which precharges a first circuit node in response to a first pulse signal and an estimation circuit that receives an input signal and a second pulse signal. The estimation circuit discharges the voltage from the first node in response to the input signal on activation of the second pulse signal. The first pulse signal is synchronized to a clock signal and the second pulse signal is delayed from the first pulse signal.

High speed flip-flop

A flip-flop includes a first circuit receiving a clock signal and the first signal and transitioning the first and second output signals to a first level when the clock signal goes to an active level, and a second circuit transitioning the first signal to the first level after the first and second output signals go to the first level. The first circuit transfers first and second input signals to the first and second output terminals from first and second input terminals when the clock signal is at the active level and the first signal is at the first level.

Flip-flops and electronic digital circuits including the same

A regulated cascode circuit includes a first PMOS FET and a second PMOS FET connected in series between a first terminal that receives a first supply voltage and an output terminal, a first NMOS FET and a second NMOS FET connected in series between the output terminal and a second terminal that receives a second supply voltage, and a regulation circuit. The regulation circuit outputs a first control signal for stabilizing a voltage at a drain of the first PMOS FET to a gate of the second PMOS FET based on a voltage of the drain of the first PMOS FET and outputs a second control signal for stabilizing a voltage change in a source of the first NMOS FET to a gate of the first NMOS FET based on a voltage of the source of the first NMOS FET.

Regulated cascode circuit, an amplifier including the same, and method of regulating a cascode circuit

A data output method and data output circuit capable of increasing data output speed by reducing clock power while increasing sensing speed are provided. The data output method includes (a) precharging output terminals to a precharge voltage lower than a supply voltage; and (b) outputting differential output signals to the output terminals in response to differential input signals. In step (a) the output terminals are precharged in response to a clock signal having a first state, and in step (b) the differential signals are output to the output terminals in response to the clock signal having a second state. The voltage swing of the clock signal is set lower than the precharge voltage. The method further includes latching the differential output signals.

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Suwon-si, South Korea

Bai-Sun Kong