Intel Corporation

Bai Nie

Kristof Darmawikarta

Sameer Paital

Robert Alan May

Gang Duan

Jesse Jones

Srinivas V Pietambaram

Rahul N Manepalli

Jeremy D Ecton

Tarek A Ibrahim

Hiroki Tanaka

Chung Kwang Christopher Tan

Omkar G Karhade

Nitin A Deshpande

Haobo Chen

Debendra Mallik

Sri Ranga Sai Boyapati

Brandon C Marin

Yonggang Li

Wei-Lun Kane Jen

Dingying David Xu

Xiaoqian Li

Changhua Liu

Jason M Gamba

Jung Kyu Han

Yosuke Kanaoka

Benjamin Duong

Aleksandar Aleksov

Sujit Sharan

James E Jaussi

Zhichao Zhang

Pooya Tadayon

Leonel R Arana

Mitul Bharat Modi

Yikang Deng

Sai Vadlamani

Hongxia Feng

Srinivas Venkata Ramanuja Pietambaram

Hari Mahalingam

Suddhasattwa Nad

Chong Zhang

Xiaoying Guo

Bharat P Penmecha

Kyle Jordan Arrington

Meizi Jiao

Marcel Arlan Wall

Arnab Sarkar

Matthew L Tingey

Divya Pratap

Kenneth Brown

Mohit Bhatia

Kemal Aygün

Suresh V Pothukuchi

Bohan Shan

Yue Deng

Rajesh Inti

Wei Wei

Santosh Tripathi

Robin Shea McRee

Susheel Jadhav

Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.

High bandwidth optical interconnection architectures

Embodiments disclosed herein include electronic packages with photonics integrated circuits (PICs). In an embodiment, an electronic package comprises a glass substrate with a first recess and a second recess. In an embodiment, a PIC is in the first recess. In an embodiment, an optics module is in the second recess, and an optical waveguide is embedded in the glass substrate between the first recess and the second recess. In an embodiment, the optical waveguide optically couples the PIC to the optics module.

Photonic interconnect and components in glass

An optoelectronic assembly is disclosed, comprising a substrate having a core comprised of glass, and a photonic integrated circuit (PIC) and an electronic IC (EIC) coupled to a first side of the substrate. The core comprises a waveguide with a first endpoint proximate to the first side and a second endpoint exposed on a second side of the substrate orthogonal to the first side. The first endpoint of the waveguide is on a third side of the core parallel to the first side of the substrate. The substrate further comprises an optical via aligned with the first endpoint, and the optical via extends between the first side and the third side. In various embodiments, the waveguide is of any shape that can be inscribed by a laser between the first endpoint and the second endpoint.

Nested glass packaging architecture for hybrid electrical and optical communication devices

Methods and apparatus to increase glass core thickness are disclosed. An example apparatus includes a first glass substrate, a second glass substrate, an interface layer between the first glass substrate and the second glass substrate, the interface layer coupling the first glass substrate to the second glass substrate, and an interconnect extending through at least a portion of the first glass substrate and at least a portion of the second glass substrate.

Methods and apparatus to increase glass core thickness

Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.

Lithographic cavity formation to enable EMIB bump pitch scaling

Various embodiments disclosed relate to methods of making omni-directional semiconductor interconnect bridges. The present disclosure includes semiconductor assemblies including a mold layer having mold material, a first filler material dispersed in the mold material, and a second filler material dispersed in the mold material, wherein the second filler material is heterogeneously dispersed.

Omni directional interconnect with magnetic fillers in mold matrix

Various embodiments disclosed relate to photonic assemblies. The present disclosure includes methods for packaging a photonic assembly, including attaching a bridge die to a glass substrate, attaching an electronic integrated circuit die to the glass substrate and the bridge die, attaching a photonic integrated circuit die to the glass substrate and the bridge die, bonding a coupling adapter to the glass substrate and in situ forming a waveguide in the coupling adapted, the waveguide aligning with the photonic integrated circuit die.

Die last and waveguide last architecture for silicon photonic packaging

Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

Microelectronic structures including bridges

A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

Patternable die attach materials and processes for patterning

Apparatuses, systems and methods associated with package substrate design with variable height conductive elements within a single layer are disclosed herein. In embodiments, a substrate may include a first layer, wherein a trench is located in the first layer, and a second layer located on a surface of the first layer. The substrate may further include a first conductive element located in a first portion of the second layer adjacent to the trench, wherein the first conductive element extends to fill the trench, and a second conductive element located in a second portion of the second layer, wherein the second conductive element is located on the surface of the first layer. Other embodiments may be described and/or claimed.

Substrate with variable height conductive and dielectric elements

Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a package substrate, a first die over the package substrate, the first die having a first bump pitch, a second die over the package substrate, the second die having a second bump pitch that is greater than the first bump pitch, and a plurality of conductive traces over the package substrate, the plurality of conductive traces electrically coupling the first die to the second die. In an embodiment, a first end region of the plurality of conductive traces proximate to the first die has a first line space (L/S) dimension, and a second end region of the plurality of conductive traces proximate to the second die has a second L/S dimension. In an embodiment, the second L/S dimension is greater than the first L/S dimension.

Hybrid fine line spacing architecture for bump pitch scaling

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Chandler, AZ, United States of America

Bai Nie