Intel Corporation

Bahaa Fahim

Yen-Cheng Liu

Robert G Blankenship

Vedaraman Geetha

Ashish Gupta

Jeffrey D Chamberlain

Debendra Das Sharma

Arvind A Kumar

Venkatraman Iyer

Raj K Ramanujan

Simon P Johnson

Robert J Safranek

Herbert H Hum

Darren S Jue

Aaron T Spink

Jeffrey Charles Swanson

Fulvio Spagna

Rahul R Shah

Jeff Willey

Robert H Beers

Sitaraman V Iyer

William Harry Nale

Abhishek Das

Yuvraj S Dhillon

Robert A Maddox

Ganapati Srinivasa

Swadesh Choudhary

Geeyarpuram N Santhanakrishnan

Samuel D Strom

Min Huang

Rahul Pal

Kai Cheng

Sridhar Muthrasanallur

Stephen R Van Doren

Kenneth C Creta

Keith Robert Pflederer

Ashok Jagannathan

Meenakshisundaram Chinthamani

Malcolm Mandviwalla

Zhiguo Wang

Krishnakumar Ganapathy

Antonio Juan

Mahesh U Wagh

Joseph Nuzman

Dean A Mulla

Adrian C Moga

Ajaya V Durg

Kent Andrew Dickey

Bongjin Jung

Riccardo Mariani

Nazar Syed Haider

Jonathan C Jasper

Gunnar Gaubatz

Tejpal Singh

Erik Hallnor

Philip Abraham

Steven R Page

Daniel W Liu

Chung-Chi Wang

Donald C Soltis, Jr

Sai Prashanth Muralidhara

Sharada Venkateswaran

Robert Steven Gottlieb

Nithiyanandan Bashyam

Jeffrey Baxter

Nishant Singh

Terry C Huang

Don C Soltis, Jr

Jason Crop

Sanilkumar Mm

Cesar Maldonado

Pau Cabre

Jonathan Jasper

Erik G Hallnor

Kent Dickey

A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

High performance interconnect

A processor includes one or more cores having cache, a cache home agent (CHA), a near memory controller, to near memory, and a far memory controller, which is to: receive a first memory read operation from the CHA directed at a memory address; detect a miss for the first memory address at the near memory; issue a second memory read operation to the far memory controller to retrieve a cache line, having first data, from the memory address of far memory; receive the cache line from the far memory controller in response to the second memory read operation; and send the cache line to the CHA with a forced change to a directory state of the cache line at the CHA, the forced change to cause the CHA to snoop remote sockets to maintain data coherence for the cache line in an absence of directory state in the far memory.

Hybrid directory and snoopy-based coherency to reduce directory update overhead in two-level memory

A processor, including a core; and a cache-coherent memory fabric coupled to the core and having a primary cache agent (PCA) configured to provide a primary access path; and a secondary cache agent (SCA) configured to provide a secondary access path that is redundant to the primary access path, wherein the PCA has a coherency controller configured to maintain data in the secondary access path coherent with data in the main access path.

Redundant cache-coherent memory fabric

In one embodiment, a processor comprises a fabric interconnect to couple a first cache agent to at least one of a memory controller or an input/output (I/O) controller; and a first cache agent comprising a cache controller coupled to a cache; and a trace and capture engine to periodically capture a snapshot of state information associated with the first cache agent; trace events to occur at the first cache agent in between captured snapshots; and send the captured snapshots and traced events via the fabric interconnect to the memory controller or I/O controller for storage at a system memory or storage device.

Method and system for cache agent trace and capture

Methods and apparatus relating to provision of core tightly coupled lockstep for high functional safety are described. In an embodiment, a master core, coupled to a slave core, executes one or more operations to support Advanced Driver Assistance Systems (ADA) or autonomous driving. The master core and the slave core receive the same input signal and core tightly couple logic causes generation of a signal in response to comparison of a first output from the master core and a second output from the slave core. The generated signal causes an interruption of the one or more operations in response to a mismatch between the first output and the second output. Other embodiments are also disclosed and claimed.

Core tightly coupled lockstep for high functional safety

Herein is disclosed an integrated input/output ('I/O') processing system, comprising an I/O port, configured to receive I/O data and to deliver the I/O data to one or more processors; one or more processors, further comprising a first processing logic and a second processing logic, wherein the one or more processors are configured to deliver the received I/O data to the first processing logic and to the second processing logic, and wherein the first processing logic and the second processing logic are configured to redundantly process the I/O data; and a comparator, configured to compare an output of the first processing logic and an output of the second processing logic.

Integrated input/output management

In an embodiment, a processor for clock signal modulation includes a clock source to generate a global clock signal, at least one processor component, a counter, and a circuit. The circuit is to: adjust the counter based on a level of activity of the at least one processor component; modulate, based on a value of the counter, the global clock signal to generate a modulated clock signal; and provide the modulated clock signal to the at least one processor component. Other embodiments are described and claimed.

Clock signal modulation for processors

A processor includes a cache-side address monitor unit corresponding to a first cache portion of a distributed cache that has a total number of cache-side address monitor storage locations less than a total number of logical processors of the processor. Each cache-side address monitor storage location is to store an address to be monitored. A core-side address monitor unit corresponds to a first core and has a same number of core-side address monitor storage locations as a number of logical processors of the first core. Each core-side address monitor storage location is to store an address, and a monitor state for a different corresponding logical processor of the first core. A cache-side address monitor storage overflow unit corresponds to the first cache portion, and is to enforce an address monitor storage overflow policy when no unused cache-side address monitor storage location is available to store an address to be monitored.

Scalably mechanism to implement an instruction that monitors for writes to an address

Operational faults, including transient faults, are detected within computing hardware for mission-critical applications. Operational requests received from a requestor node are to be processed by shared agents to produce corresponding responses. A first request is duplicated to be redundantly processed independently and asynchronously by distinct shared agents to produce redundant counterpart responses including a first redundant response and a second redundant response. The first redundant response is compared against the second redundant response. In response to a match, the redundant responses are merged to produce a single final response to the first request to be read by the requestor node. In response to a non-match, an exception response is performed.

Mission-critical computing architecture

A cache controller id disclosed, The cache controller includes circuitry to receive a request to access data in a target location of a last level cache of a processor on a processor package, identify an in-field failure in the target location of the last level cache, perform, in response to the identification of the in-field failure, an in-field repair, including circuitry to write in-field repair information to a non-volatile memory on the processor package and external to the processor, the non-volatile memory including circuitry to store in-field repair information. Systems and methods are also disclosed.

System and method for granular in-field cache repair

System, method, and processor for enabling early deallocation of tracker entries which track memory accesses are described herein. One embodiment of a method includes: maintaining an RSF corresponding to a first processing unit of a plurality of processing units to track cache lines, wherein a cache line is tracked by the RSF if the cache line is stored in both a memory and one or more other processing unit, the memory is coupled to and shared by the plurality of processing units; receiving a request to access a target cache line from a processing core of the first processing unit; allocating a tracker entry corresponding to the request, the tracker entry used to track a status of the request; performing a lookup in the RSF for the target cache line; and deallocating the tracker entry responsive to a detection that the target cache line is not tracked the RSF.

Optimized caching agent with integrated directory cache

Growing community of inventors

Santa Clara, CA, United States of America

Bahaa Fahim