International Business Machines Corporation

Alcedo, Inc.

Badih El-Kareh

James Gardner Ryan

Stanley Everett Schuster

Ashwin K Ghatalia

William R Tonti

Wendell P Noble

Wayne Frederick Ellis

Wagdi William Abadeer

Richard Anthony Conti

Josef S Watts

Carter W Kaanta

Matthew J Rutten

Richard L Kleinhenz

Stephen Bruce Brodsky

Duane E Galbi

Nathan R Hiltebeitel

Eric D Johnson

Karanam Balasubramanyam

Stuart R Martin

Sridhar Divakaruni

Terry J Brabazon

Jack Allan Mandelman

Gary Bela Bronner

Russell J Houghton

John E Gersbach

Hiroyoshi Tanimoto

Stephen A Parke

Paul E Cade

Richard R Garnache

Auguste B El-Kareh

Ick W Kim

A metal interconnect having a high conductivity and high resistance to metal migration failure is formed of two layers of metal or alloy (such as TI/CuAlSi) with a dielectric interposed therebetween and a connection made between the layers by a conductive material, preferably in the form of a plug or stud formed in an aperture of an inter-level dielectric, at ends of the interconnect. A high precision metal-to-metal capacitor can be formed from the same layers by forming separate connections to each of the layers. The topography of the interconnect (and capacitor) is of reduced severity and facilitates planarization of an overlying inter-level dielectric.

Flexible interconnections with dual-metal dual-stud structure

A system for detecting charge accumulation during semiconductor wafer manufacturing including a sensor comprising a capacitor, an emitter for directing a primary electron beam toward the sensor, wherein the primary electron beam causes the sensor to emit secondary electrons and a detector for measuring the secondary electrons.

Capacitor charging sensor

A MOSFET device is formed on a P- doped semiconductor substrate with an N- well formed therein, with a pair of isolation regions formed in the N- well with a gate oxide layer formed above the N- well. An FET device is formed with source and drain regions within the N-well, and a gate electrode formed above the gate oxide layer aligned with the source and drain regions. The gate electrode comprises a stack of layers. A polysilicon layer is formed on the gate oxide layer. A tungsten nitride dopant barrier layer is formed upon the polysilicon layer having a thickness of from about 5 nm to about 20 nm, and a tungsten silicide layer is formed upon the tungsten nitride layer.

Controlled dopant diffusion and metal contamination in thin polycide

A method of forming integrated circuit chips including two dissimilar type NFETs and/or two dissimilar type PFETs on the same chip, such as both thick and thin gate oxide FETs. A DRAM array may be constructed of the thick oxide FETs and logic circuits may be constructed of the thin oxide FETs on the same chip. First, a gate stack including a first, thick gate SiO.sub.2 layer is formed on a wafer. The stack includes a doped polysilicon layer on the gate oxide layer, a silicide layer on the polysilicon layer and a nitride layer on the silicide layer. Part of the stack is selectively removed to re-expose the wafer where logic circuits are to be formed. A thinner gate oxide layer is formed on the re-exposed wafer. Next, gates are formed on the thinner gate oxide layer and thin oxide NFETs and PFETs are formed at the gates. After selectively siliciding thin oxide device regions, gates are etched from the stack in the thick oxide device regions. Finally, source and drain regions are implanted and diffused for the thick gate oxide devices.

Method for dual gate oxide dual workfunction CMOS

An optimized trench capacitor structure which is useful as a decoupling capacitor or a storage capacitor can be manufactured without added process complexity. As an on-chip decoupling trench capacitor structure, the structure reduces the series resistance to outer and inner plates and results in an acceptable RC delay, while maintaining a high capacitance per unit area. As a storage capacitor with a buried shield, the trench capacitor structure exhibits high immunity to alpha particle and cosmic radiation induced failures. The trench capacitor structure which includes a buried n-well in a silicon substrate. A trench is formed in the substrate and extends through the buried n-well. A dielectric film is formed on an inner surface of the trench, and an inner plate formed as a polysilicon fill within the trench is connected to a surface n+ film formed during definition of peripheral source/drain contacts of the integrated circuit. An outer plate of the capacitor in the form of an out diffusion from the trench provides a low resistance electrical contact with the substrate. A number of these capacitors can be combined in a very efficient X-Y array of decoupling capacitors.

Trench capacitor structures

A semiconductor structure comprising a transistor having a gate conductor that has first and second edges bounded by raised isolation structures (e.g. STI). A source diffusion is self-aligned to the third edge and a drain diffusion is self-aligned to the fourth edge of the gate electrode.

Method for fabricating a MOSFET with raised STI isolation self-aligned

A precision analog metal-metal capacitor is fabricated by forming a first capacitor plate in an insulation layer by forming a trench therein, depositing metal within the trench and planarizing the device. A thin dielectric layer is then deposited and patterned over the first capacitor plate. A second insulator is then deposited over the device and discrete openings etched therein to expose the insulation layer and first metal plate. Metal is deposited within the openings and planarized, thereby forming a contact to the first metal plate and the second metal plate of the capacitor.

Precision analog metal-metal capacitor

Method of making flexible interconnections with dual-metal-dual-stud

An ESD protective device is formed having a repeatable gap dimension for reliable protection by the formation of a discharge, using the materials of the gate stack for economy and a sacrificial dielectric formed between the plug and the other terminal for repeatable definition of a discharge gap.

Method for electrostatic discharge protection through electric field

Method of controlling dopant diffusion and metal contamination in thin

According to the preferred embodiment, a defect monitor is provided that uses a floating gate structure. The defect monitor includes a common source, a common drain, and a plurality of floating gates interdispersed between the source and drain. Additionally, a conductor covers the plurality of floating gates. By applying a bias to the conductor and measuring the current flowing through the drain and source, the distribution of defects on the semiconductor wafer can be estimated.

Floating gate interlevel defect monitor and method

The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to decrease the latch-up susceptibility of an ESD structure by suppressing the injection of minority carriers that cause transistor action to occur. This is accomplished, for example, by using a metal contact to the n-substrate or n-well in place of or in parallel with the prior art p-diffusion. Using such a metal contact forms a Schottky Barrier Diode (SBD) with the ESD structure. Since the SBD is a majority-carrier device, negligible minority carriers are injected when the SBD is in forward bias, thereby reducing the likelihood of latch-up.

ESD structure that employs a schottky-barrier to reduce the likelihood

MOSFET with raised STI isolation self-aligned to the gate stack

Growing community of inventors

Austin, TX, United States of America

Badih El-Kareh