Zenith Electronics Corporation

Zenith Data Systems Corporation

Zenith Radio Corporation

Babu Rajaram

Anthony M Olson

Charles A Krause

Mark J Foster

Thomas N Robinson

Gregg Chandler

Barry A Watzman

A computer system includes a memory capable of storing a plurality of data words, and a central processing unit for outputting data words to be stored in the memory. A method and apparatus for facilitating transfer of the data words from the central processing unit to the memory involve accepting and temporarily storing in a storage portion each data word from the central processing unit and then subsequently storing in the memory each temporarily stored data word, the maximum number of data words which can be temporarily stored being selectively set to one of first and second values which are different.

Variable size queue circuit for buffering data transfers from a

In response to an address decoded in a preselected range, a multiplexer combines translated high order address bits with CPU-generated low order address bits to access random access memory, especially reserved range random access memory. Otherwise, the multiplexer merely combines CPU-generated low order bits with CPU-generated high order address bits to access RAM. An expanded memory specification memory map drives the translator to generate the translated high order address bits. This generates the address for reserved range RAM. RAM contents, normal and reserved range, are available for processing by the CPU.

Method of combining lower order and translated upper order bits to

Four parallel, spaced arrays of apertures are provided in a printed circuit (PC) board to accommodate mounting of 16- and 18-pin dynamic random access memories (DRAMs) within a minimum area footprint. First and second 8-aperture linear arrays are provided in the PC board in spaced relation to accommodate 16-pin DRAMs as are third and fourth 9-aperture linear arrays to accommodate 18-pin DRAMs, wherein the third and fourth arrays of apertures are aligned parallel with and respectively positioned intermediate and outside of the first and second arrays of apertures in the PC board. Corresponding apertures in the 16- and 18-aperture arrays for receiving corresponding pins of the 16- and 18- pin DRAMs are electrically coupled, with the two additional apertures of the 18-aperture array extending beyond the 16-aperture array and aligned therewith. The limited footprint area is thus capable of receiving, mounting and electrically coupling in circuit either a 16-pin or an 18-pin DRAM or any integrated circuit having a dual-in-line pinout configuration.

Mounting of DRAMs of different sizes and pinouts within limited footprint

An improved method for refreshing dynamic random access memory devices is disclosed. Normal refresh clocking signals are monitored and a count accumulated up to a selected value. Refresh operations are then initiated less frequently and only when the selected count has been accumulated. Once control of the bus to the memory has been achieved, a burst of refresh operations are performed prior to release of the bus. Improved efficiency and operating speed may be achieved by minimizing wasted time associated with acquisition and control of the bus. A preferred embodiment illustrates savings associated with a burst of four refresh operations each time the bus to the memory device is acquired for refreshing. Page addressing techniques are enhanced by forcing a change of state of the row address strobe line bus frequently than typical refresh operations.

Burst refresh of dynamic random access memory for personal computers

Page mode memory access is enabled despite an immediately previous idle cycle. A row address strobe signal is maintained active during an idle cycle so that if a page hit is detected on a subsequent memory cycle, all that is needed to read or write to memory is a column address strobe signal which can be provided via a page mode access. In this manner, memory speed is enhanced because a conventional access is not required on the first memory cycle following one or more idle cycles.

Method for improving the page hit ratio of a page mode main memory system

A data processing system includes a high speed buffer, or cache, memory for temporarily storing recently executed instructions and a slower main memory in which is stored the system's operating program. Rather than sequentially accessing the cache memory to determine if the next instruction is stored therein and then accessing the main memory if the cache memory does not have the next instruction, system operating speed is increased by simultaneously accessing the cache and main memories. By accessing the main memory during its row address strobe (RAS) precharge time while simultaneously accessing the cache memory, the time necessary for the system's processor unit (PU) to read the next instruction from the main memory when not stored in the cache memory is substantially reduced.

Main memory access in a microprocessor system with a cache memory

A data processing system includes a plurality of memory access devices, each having a characteristic operating speed, for writing data into and reading data from a dynamic random access memory (DRAM) as well as a memory controller for accessing a plurality of addressable storage locations in the DRAM for either storing data in or reading stored data from the various storage locations in the DRAM. The system further includes a dynamic column address strobe (CAS) signal generator responsive to a memory access cycle signal, or READ pulse, and a conventional CAS signal for generating a dynamic CAS signal having a floating trailing edge which extends to the end of the memory access cycle as well as to the trailing edge of the READ pulse irrespective of the length of the memory access cycle signal to allow data to be read from the DRAM by any memory access device regardless of its operating speed during a memory access signal without losing or temporarily storing this data prior to providing it to the memory access device.

Data processing system with extended memory access

In a dual microprocessor system, a processor transfer, or swap, arrangement and method therefor are disclosed for transferring control from one processor to another. The present invention involves the temporary suspension of operation of a first microprocessor which relinquishes system control and the initiation of operation of a second microprocessor which may begin operation either where it last left off or may execute a new operating routine in accordance with instructions provided by the first microprocessor. Provision is made for automatically handing over system control to the second microprocessor upon the occurrence of an interrupt. In addition, the microprocessor not exercising system control is rendered unresponsive to the occurrence of a program interrupt allowing it to continue opration unaffected by the program interrupt following its reactivation. -

Switchcover means and method for dual mode microprocessor system

In a video display system having a video random access memory (RAM) including a plurality of color memory banks, with one memory bank for each of the primary colors, provision is made for simultaneously writing to all of the color banks. A central processor unit (CPU) places data onto the system bus and asserts WRT-R, WRT-G and/or WRT-B signals in selectively writing at the same time to any or all of the video RAM banks, where the primary colors are red, green and blue. Logic circuitry coupled to the three RAM banks then gates designated Row and Column Address Strobe (RAS and CAS) signals to each of the color arrays followed by color video data signals. The time required to thus write video display information into the multi-bank video RAM array is thus reduced and system video data throughput correspondingly increased.

Multi-bit write feature for video RAM

Conventional bit-mapped address locations in a character oriented video random access memory (RAM) in which each character is represented by a bit mapping array comprised of ten lines each including eight pixels, or eight bits of information, in an X-Y matrix address organization are redefined in terms of the character and row address locations of a graphics oriented cathode ray tube controller for driving a video display. Groups of bits in the X-Y matrix address locations of the video RAM are shifted in a predetermined manner in generating a redefined, 1:1 mapping function addressing code which is provided to a cathode ray tube controller for driving the video display. A video RAM mapping module is provided for reorganizing the video RAM addresses and translating these addresses throughout the page of the video RAM in providing more efficient graphics mapping while retaining high resolution alphanumeric character video resolution. In one embodiment, a video display start bit is incremented by an 8-bit adder to provide for scrolling on a line-by-line basis without moving character bytes from one location to another in the video RAM.

Character oriented RAM mapping system and method therefor

A video display system utilizes three banks of memory for producing an 8-color or an 8-level gray scale display. A separate memory plane, or random access memory (RAM) array, for each of the 'primary' video colors, i.e., red, green and blue, is used in a bit-mapped video graphics implementation for a computer driven video display. In a monochrome display, pixel mixing produces the 8-level gray scale display. Each of the video planes may be selectively disabled as desired for special applications. For example, a limited animation capability may be provided by displaying one page while generating a new page in a non-displayed page. By disabling the currently displayed plane as the new plane is enabled, instantaneous page modification may be closely simulated for animated applications. The thus disabled video plane may then be used as any normal page of RAM for any other application. In addition, all of the video RAM planes may be disengaged from the central processing unit (CPU) to blank the video display for various applications such as during initial system reset or as part of an operating program.

Selective page disable for a video display

A system for resolving the contention between the central processing unit (CPU) and the cathode ray tube (CRT) controller in accessing the video memory array, or video random access memory (RAM), of a data processing system is disclosed. The conventional CPU-CRT controller accessing sequence is modified to provide a CPU access period between successive CRT controller access periods. In addition, arbitration logic is included to provide CRT controller access priority when there is contention between the CPU and the CRT controller. By thus assigning video memory access priority to the CRT controller and increasing the length of the video memory array 'read' time during which video information is provided to the system's display device, video display performance is enhanced and display degradation due to video memory array operating speed limitations is essentially eliminated. This approach reduces operating speed criteria of the various components in the data processing system in providing high quality display graphics and improved system operating functions without the need for highly sophisticated and expensive CPU's, RAM's, etc.

Growing community of inventors

St. Joseph, MI, United States of America

Babu Rajaram