International Business Machines Corporation

Philips Electronics North America Corporation

North American Philips Corporation

Tektronix, Inc.

Other

U.S. Philips Corporation

Globalfoundries Inc.

Koninklijke Philips Corporation N.v.

Philips Electronics N.a. Corporation

Babar Ali Khan

Jacob Bruinink

Karel E Kuijk

Xinhui Wang

Herbert Lei Ho

Adrianus Leonardus Burgmans

Petrus Franciscus Bongaerts

Effendi Leobandung

Kevin K Chan

Henri R Van Helleputte

Theodorus E Standaert

Sivananda K Kanakasabapathy

John Edward Barth, Jr

Masaharu Kobayashi

Ronald D Pinker

David A Cammack

Nikhil R Taskar

Thomas S Buzak

Kevin J Ilcisin

Paul C Martin

Kirk David Peterson

Subramanian Srikanteswara Iyer

Kangguo Cheng

Joel Pereira De Souza

Henri R J R Van Helleputte

Arvind Kumar

Paul Christian Parries

Edward H Stupp

Donald R Dorman

Petrus F G Bongaerts

Adrianus L J Burgmans

Devendra K Sadana

Bruce Bennett Doris

Ning Li

Chandrasekharan Kothandaraman

Anthony J Annunziata

John Ryan Sporre

Yun Seog Lee

Emily R Kinser

Oh-Jung Kwon

Ricardo Alves Donaton

Joyce C Liu

Vivek Mehrotra

Deepal Wehella-Gamage

Ali Khakifirooz

Takashi Ando

Carl John Radens

Shom Ponoth

Soon-Cheon Seo

Geng Wang

Reinaldo Ariel Vega

Kern Rim

Chengwen Pei

Eduard Albert Cartier

Hiroyuki Miyazoe

Dae-Gyu Park

Rama Divakaruni

Ravi Mahendra Todi

Dexin Kong

Abhishek Dube

Ashima B Chakravarti

Christopher Carr Parks

Kehan Tian

Youngseok Kim

Andrew A Turner

Junedong Lee

Gerd Pfeiffer

Jerry Martin Kramer

Chandrasekara Kothandaraman

John B DeForge

Piotr M Mensz

Jennifer E Appleyard

Huilong Zhu

Veeraraghavan S Basker

Ramachandra Divakaruni

Hemanth Jagannathan

Ravikumar Ramachandran

Robert C Wong

Kamal Kumar Sikka

Christopher Joseph Waskiewicz

Johnathan E Faltermeier

Nathan P Marchack

Byeong Yeol Kim

David M Dobuzinsky

Peter J Janssen

Robert Hannon

William J Cote

Tzyy-Ming Cheng

Deok-kee Kim

Xi Li

Chienfan Yu

Russell Herbert Arndt

Philip L Flaitz

John W Golz

Thomas A Wallner

Yoichi Otani

Teresa Jacqueline Wu

Sundar Kumar Iyer

John E Barth

Kai Xiu

A method for filtering magnetic particles includes spinning a filter including a plurality of pores within a substrate. The method further includes applying, subsequent to spinning the filter, an external magnetic field to the filter. The method includes disposing a solution including a first particle and a second particle onto the filter. The first particle includes a magnetic particle of interest. The method further includes separating the first particle from the second particle by capturing the first particle within a pore of the plurality of pores within the substrate.

Micro-machined filter for magnetic particles

Embodiments of the invention provide a resistive switching device that includes a metal interconnect electrode and a charge-particle-treated memory stack over the metal interconnect electrode. The charge-particle-treated memory stack includes a plurality of layers that includes a top electrode, a bottom electrode, and a dielectric layer between the top electrode and the bottom electrode. The dielectric layer includes a portion of a blanket dielectric layer. The bottom electrode includes a portion of a blanket bottom electrode layer. The charge-particle-treated memory stack further includes a current-conducting filament characteristic that results from charge particle treatments applied while a top surface of the blanket dielectric layer is exposed and a top surface of the blanket bottom electrode is exposed.

Oxide-based resistive memory having a plasma-exposed bottom electrode

Provided are embodiments for a semiconductor device. The semiconductor device includes a bottom electrode, wherein the bottom electrode is formed on a metal interconnect electrode, and a dielectric layer on a surface of the bottom electrode. The semiconductor device also includes a top electrode formed on a surface of the dielectric layer, wherein at least one of the top electrode or the bottom electrode is a plasma treated top electrode or plasma treated bottom electrode. Also provided are embodiments for a method of fabricating a resistive switching device where at least one of the plurality of layers of the memory stack is processed with a charge particle treatment.

A semiconductor device includes a field-effect transistor, a first back-end-of-line (BEOL) metallization level and a second BEOL metallization level disposed above the first BEOL metallization level. A portion of the field-effect transistor includes lithium therein, and the field-effect transistor is integrated between the first and second BEOL metallization levels. The portion of the field-effect transistor including the lithium therein can be a channel layer, or a source and/or drain region.

Lithium drifted thin film transistors for neuromorphic computing

Embodiments of the invention are directed to a resistive switching device (RSD). A non-limiting example of the RSD includes a fin-shaped element formed on a substrate, wherein the fin-shaped element includes a source region, a central channel region, and a drain region. A gate is formed over a top surface and sidewalls of the central channel region. The fin-shaped element is doped with impurities that generate interstitial charged particles configured to move interstitially through a lattice structure of the fin-shaped element under the influence of an electric field applied to the RSD.

FinFET resistive switching device having interstitial charged particles for memory and computational applications

An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

Semiconductor structures with deep trench capacitor and methods of manufacture

A computing device includes a wafer having multiple layers, the wafer including a top layer and sublayers disposed below it, the sublayers including one or more memory devices. The computing device also includes two or more shaped retainer elements shaped to mate with and at least partially surround at least the top of the wafer and in electrical contact with one or more chips disposed on a top of the top layer and a holding device that mates with the retainer elements to provide at least power to the retaining elements. So arranged, the wafer may be cooled.

Cooling and power delivery for a wafer level computing board

A magnetic tunnel junction (MTJ) containing device and methods of constructing the MTJ containing device are described. In an example, the MTJ containing device may be a memory element including a bottom electrode structure, a MTJ pillar, and a top electrode structure located on the MTJ pillar. The MTJ pillar has a non-circular lateral cross section, where the MTJ pillar has a bottommost portion forming an interface with an uppermost portion of the bottom electrode structure. The MTJ pillar has a lateral perimeter-to-area ratio that defines a breakdown voltage of the MTJ pillar.

OTP elements with high aspect ratio MTJ

Methods of forming the MRAM generally include forming an array of MTJ having sub-lithographic dimensions. The array can be formed by providing a substrate including a MTJ material stack including a reference ferromagnetic layer, a tunnel barrier layer, and a free ferromagnetic layer on an opposite side of the tunnel barrier layer. A hardmask layer is deposited onto the MTJ material stack. A first sidewall spacer is formed on the hardmask layer in a first direction. A second sidewall spacer is formed over the first sidewall in a second direction, wherein the first direction is orthogonal to the second direction. The second sidewall spacer intersects the first sidewall spacer. The first sidewall spacer is processed using the second sidewall spacer as mask to form a pattern of oxide pillars having sub-lithographic dimensions. The pattern of oxide pillars are transferred into the MTJ stack to form the array.

Sub-lithographic magnetic tunnel junctions for magnetic random access memory devices

An integrated FinFET and deep trench capacitor structure and methods of manufacture are provided. The method includes forming deep trench capacitor structures in a silicon on insulator (SOI) wafer. The method further includes forming a plurality of composite fin structures from a semiconductor material of the SOI wafer and conductive material of the deep trench capacitor structures. The method further includes forming a liner over the deep trench capacitor structures including the conductive material of the deep trench capacitor structures. The method further includes forming replacement gate structures with the liner over the deep trench capacitor structures protecting the conductive material during deposition and etching processes.

Growing community of inventors

Ossining, NY, United States of America

Babar Ali Khan