Qualcomm Incorporated

Quantenna Communications, Inc.

On Semiconductor Connectivity Solutions, Inc.

Babak Soltanian

Jafar Savoj

Sigurd Schelstraete

Sam Heidari

Richard Kinder

Ali Rouhi

James Herbert

Stephane Cattet

Vahbod Pourahmad

Hong Sun Kim

A wireless access point (WAP) configured to supporting wireless communications with station nodes on a selected communication channel of an associated wireless local area network (WLAN). The WAP includes multiple multiple-input multiple-output (MIMO) transmit and receive paths. The WAP is to intermittently switch one of the multiple MIMO receive paths to concurrently process both communications on a selected communication channel together with monitoring communications on unselected channels of the multiple communication channels associated with the WLAN.

Channel tracking in a wireless home network

A wireless access point (WAP) configured to support a wireless home network among multiple wireless devices over a shared wireless communication medium on a selected channel. In an embodiment of the invention the WAP includes a channel tracker configured to track performance metrics over time for at least the selected channel; and to predict based on the tracked performance metrics at least one of: a predicted time of an impending channel changeover requirement in which a projected demand for the selected channel exceeds a projected capacity thereof and a predicted time of an impending monitoring interval for monitoring an unselected channel with relatively minimal disruption of communications on the selected channel. In another embodiment of the invention the WAP includes receive path components configured to concurrently process both communications on the selected channel together with monitored communications on an unselected channel.

A VCO of a PLL outputs a first differential signal of frequency FVCO. A first divide-by-two circuit local to the VCO divides the first differential signal and outputs a first quadrature signal of frequency FVCO/2. Two of the component signals of the first quadrature signal are routed to a second divide-by-two circuit local to a first mixer of a first device. The second divide-by-two circuit outputs a second quadrature signal of frequency FVCO/4 to the first mixer. All four signals of the first quadrature signal of frequency FVCO/2 are routed through phase mismatch correction circuitry to a second mixer of a second device. In one example, FVCO is a tunable frequency of about ten gigahertz, the first device is an IEEE802.11b/g transmitter or receiver that transmits or receives in a first band, and the second device is an IEEE 802.11a transmitter or receiver that transmits or receives in a second band.

LO generation and distribution in a multi-band transceiver

A VCO of a PLL outputs a first differential signal of frequency FVCO. A first divide-by-two circuit local to the VCO divides the first differential signal and outputs a first quadrature signal of frequency FVCO/2. Two of the component signals of the first quadrature signal are routed to a second divide-by-two circuit local to a first mixer of a first device. The second divide-by-two circuit outputs a second quadrature signal of frequency FVCO/4 to the first mixer. All four signals of the first quadrature signal of frequency FVCO/2 are routed through phase mismatch correction circuitry to a second mixer of a second device. In one example, FVCO is a tunable frequency of about ten gigahertz, the first device is an IEEE802.11b/g transmitter or receiver that transmits or receives in a first band, and the second device is an IEEE802.11a transmitter or receiver that transmits or receives in a second band.

A quadrature output high-frequency RF divide-by-two circuit includes a pair of differential complementary logic latches. The latches are interconnected to form a toggle flip-flop. Each latch includes a tracking cell and a locking cell. In a first embodiment, the locking cell includes two complementary logic inverters and two transmission gates. When the locking cell is locked, the two gates are enabled such that the locked (i.e., latched) signal passes through both transmission gates and both inverters. In one advantageous aspect, the tracking cell only involves two transmission gates. Due to the circuit topology, the first embodiment is operable from a low supply voltage at a high operating frequency while consuming a low amount of supply current. In a second and third embodiment, the tracking cell involves a pair of inverters. The sources of the transistors of the inverters are, however, coupled together thereby resulting in performance advantages over conventional circuits.

Low power complementary logic latch and RF divider

Techniques for designing a high performance analog switch for use in electronic circuit applications. In one aspect, a variable bulk voltage generation module is provided to vary the bulk voltage of a transistor in the switch, such that the threshold voltage of the transistor is reduced during the on state. In another aspect, a pulling transistor is provided to pull a middle node of the switch to a DC voltage during the off state to further increase the isolation provided by the switch.

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San Jose, CA, United States of America

Babak Soltanian