Hewlett-packard Company

Hewlett-packard Development Company, L.P.

Hitachi, Ltd.

B Ramakrishna Rau

Michael S Schlansker

Shail Aditya Gupta

Vinod Kumar Kathail

Rajiv Gupta

Robert S Schreiber

William S Worley, Jr

Frederic C Amerson

Naohiko Irie

Santosh Abraham

Yooichi Shintani

Yoshikazu Tanaka

Joseph A Fisher

Richard C Johnson

Sadun Anik

Design spaces for systems, including hierarchical systems, are programmatically validity filtered and quality filtered to produce validity sets and quality sets, reducing the number of designs to be evaluated in selecting a system design for a particular application. Validity filters and quality filters are applied to both system designs and component designs. Component validity sets are combined as Cartesian products to form system validity sets that can be further validity filtered. Validity filters are defined by validity predicates that are functions of discrete system parameters and that evaluate as TRUE for potentially valid systems. For some hierarchical systems, the system validity predicate is a product of component validity predicates. Quality filters use an evaluation metric produced by an evaluation function that permits comparing designs and preparing a quality set of selected designs. In some cases, the quality set is a Pareto set or an approximation thereof.

Programmatic design space exploration through validity filtering and quality filtering

A method for the automatic design of processor datapaths operates on an abstract input specification of desired processor operations and their instruction level parallelism and synthesizes a datapath design in machine readable form. A datapath synthesizer automatically designs and synthesizes the processor datapath including the number and types of functional units, the number of read/write ports of the various register files, and the exact connectivity between the register files and the functional units. The heuristics used in the implementation maximize resource sharing and minimize the overall cost in by customizing and sharing functional units and minimizing the number of read/write ports on the register files subject to the specified ILP among operations.

Automatic design of processor datapaths

A VLIW processor design system automates the design of programmable and non-programmable VLIW processors. The system takes as input an opcode repertoire, the I/O format of the opcodes, a register file specification, and instruction-level parallelism constraints. With this input specification, the system constructs a datapath, including functional units, register files and their interconnect components from a macrocell database. The system uses the input and the datapath to generate an instruction format design. The instruction format may then be used to construct the processor control path. The abstract input and datapath may be used to extract a machine description suitable to re-target a compiler to the processor. To optimize the processor for a particular application program, the system selects custom instruction templates based on operation issue statistics for the application program generated by the re-targeted compiler.

Automatic design of VLIW processors

A programmatic method transforms a nested loop in a high level programming language into a set of parallel processes, each a single time loop, such that the parallel processes satisfy a specified design constraint. Another programmatic method synthesizes a processor array from the set of parallel processes and a specified design constraint.

Programmatic synthesis of processor element arrays

An automated method for designing a processor's control path employs program routines that synthesize the control path based on the processor's instruction format and data path specification. It extracts parameters from a machine-readable description of the processor's instruction format, and generates a specification of the components in the control path and their interconnection with the control ports in the data path.

Automated design of processor instruction units

A computer-implemented method automates the design of efficient binary instruction encodings of VLIW instruction formats. The method automatically finds compact instruction formats that can express and exploit the full parallelism specified in the underlying processor microarchitecture, subject to constraints on alignment and decode hardware complexity. The method can be guided by statistics about the composition and frequency of program instructions, so that the instruction format design is customized to a particular set of applications or an application domain.

Automatic design of VLIW instruction formats

Auto design of VLIW processors

A computer system provides fast evaluation of predicates and Boolean expressions with a set of operations for determining a value in a specified register from a plurality of inputs. The execution of each operation is defined by two functions of the operation's inputs: a result function which yields a result value, and an enable function which determines whether the result value is written to the specified register. To evaluate a Boolean expression with the operations, the register is preset to a Boolean value, e.g. one for an AND reduction, zero for an OR reduction. The operations can then write a Boolean value, e.g. zero for an AND reduction, one for an OR reduction, to the register if each operation's enable function evaluates true. The register then stores the correct value of the expression. The expression's value can be used as predicates to conditionally execute operations in a program. Preferably, the operations are executed in parallel by plural functional units, and the register is capable of accepting multiple values written simultaneously, so long as they are identical.

Computer system and method for evaluating predicates and Boolean

A method for supporting speculative execution includes designating operations as speculative or non-speculative, and then deferring exceptions generated by speculative operations while immediately reporting exceptions by non-speculative operations. If a speculative operation uses a result of a speculative operation that has generated an exception, the exception is propagated. Deferred exceptions are detected and reported using a check operation either incorporated into a non-speculative operation or inserted as a separate check operation. A system for supporting speculative execution includes a functional unit for recognizing a speculative operation and deferring any exceptions generated by such an operation. The functional unit may defer an exception by storing information indicating an error has occurred in the register file. To check for deferred exceptions, the functional unit then reads the register file. If an exception is detected, then the exception is processed and one or more of the speculative operation are re-executed (in a non-speculative mode) where necessary to process the exception.

Method and system for propagating exception status in data registers and

To improve the function of a circuit for prefetching data accessed by a processor, a prefetch unit incorporates therein a circuit for issuing a request to read out one group of data to be prefetched and registers for holding the group of data read in response to the read request therein. The group of data are read out from a cache memory or a main memory under the control of a cache request unit. A plurality of groups of data can be prefetched. When data designation is made, the processor requests the cache memory to read a block to which the data to be prefetched belongs. A circuit is also included in the prefetch unit, wherein when prefetched data is subsequently updated by the processor, its updated data is made invalid. Elements of a vector complex in structure, such as an indexed vector or the like can be also read out. It is also possible to cope with an interrupt generated within the processor.

Information processing apparatus with prefetch control for prefetching

A method and system are disclosed which allow a computer program to execute properly in object code compatible processing systems which have latencies different from those with which the program was created or compiled. This resulting compatibility of the computer program is achieved because the invention protects the precedence of operations within the computer program using latency assumptions which were used when creating the computer program. When the computer program is created, latency assumption information is efficiently provided within the computer program. Thereafter, when the computer program is executed, it is able to advise the processing system of the latency assumptions with which it was created. Various ways are described in which the processing system can utilize the latency assumptions when executing the computer program so as to ensure compatibility.

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Los Altos, CA, United States of America

B Ramakrishna Rau