National Instruments Corporation

B Keith Odom

Kevin L Schultz

Robert Wayne Hormuth

Craig M Conway

Bob Mitchell

Glen Sescila

Charles G Schroeder

Ross Sabolcik

Hugo A Andrade

Cary Paul Butler

Rodney W Cummings

Arthur M Ryan

Mike Hall

A system and method for acquiring images of variably sized objects. An object detector provides an indication of the presence or absence of objects as they pass by. An image sensing device acquires image data for the objects. An image acquisition device starts an activity counter, and initiates storage of image data for an object in response to detecting presence of the object. The image data is stored into an on-board memory. The activity counter counts a number of acquired scan lines for the object. In response to detecting absence of the object, the image acquisition device terminates the activity counter, and discontinues storage of the image data for the object. The final activity counter value, which reflects the number of scan lines acquired for the object, is recorded in an on-board FIFO. The image data is transferred to a system memory image buffer in a system memory. Host software routines may read the on-board FIFO. The image acquisition device is configured to rearm for acquisition of another object by resetting the activity counter, and initializing a write pointer to the on-board memory so that it points to the top of a next on-board memory buffer. After rearming, the image acquisition device may acquire image data for a second object in response to detecting presence of the second object.

Image acquisition system and method for acquiring variable sized objects

A video capture system and method whereby video frames or images, which are received in one of a plurality of possible formats, are acquired and stored into on-board memory in an image format. The image data can then be transferred into system memory at an optimum rate. The video capture system comprises a host computer, including a video capture board, which is coupled to a video source, such as a video camera. The video source provides digital video data in a first format of a plurality of different possible formats. The video capture board includes a memory controller which receives the digital video data in the first format and selectively provides the digital video data to the buffer memory in an image format. The memory controller includes address generation logic for generating buffer memory addresses for storing the video data to the buffer memory in the image format. The address generation logic is programmable with configuration information corresponding to the first format and uses the configuration information to generate the addresses.

Video acquisition system including a virtual dual ported memory with adaptive bandwidth allocation

A modular telecommunication test system is presented including a portable computer system and at least one portable telecommunication test module located external to the computer system. The portable computer system stores a telecommunication test application (e.g., in a memory system). Each test module includes a communication port having an electrical connector, and is thus adapted for coupling to the portable computer system. Each test module also includes electrical circuitry for performing a set of telecommunication tests, wherein each test involves making at least one electrical measurement upon a telecommunication service installation. In coupling a given test module to the portable computer system, a user configures the test system to perform the set of telecommunication tests associated with the given test module. The at least one test module is selected from a group of test modules, each configured to perform telecommunication tests upon a different type of telecommunication service installation. Eligible types of telecommunication service installations include POTS, T1/E1, ISDN, and xDSL. The test system may also include a second computer system (e.g., a desktop computer system) coupled to the first computer system via a communication network. The communication network may include the PSTN and the Internet. The first computer may receive telecommunication test data from each test module and provide the test data to the second computer system via the communication network.

System and method for testing telecommunication service installations

A Wide Area Serial PCI system for connecting peripheral devices to a computer. The WASP system includes a host computer system connected through a serial bus to a remote device. The serial bus can range from several meters to several kilometers or more. The host computer system includes a CPU and memory, and also includes a first Peripheral Component Interconnect (PCI) bus, also referred to as the local PCI bus. A primary bridge according to the present invention is coupled to the first PCI bus. The primary bridge includes PCI interface circuitry for interfacing to the first PCI bus. The remote device is located remotely from the computer system and comprises a second or remote PCI bus and one or more peripheral devices coupled to the second PCI bus. The remote device also includes a secondary bridge coupled to the second PCI bus. The secondary bridge includes PCI interface circuitry for interfacing to the second PCI bus. The serial bus is coupled between the primary bridge and the secondary bridge. Each of the primary bridge and secondary bridge include parallel/serial transceivers for converting parallel data generated on the first PCI bus and second PCI bus, respectively, to serial data for transmission on the serial bus and for converting serial data received from the serial bus to parallel data for generation on the first PCI bus and second PCI bus, respectively. The primary bridge and the secondary bridge collectively implement a PCI&mdash;PCI bridge register set.

System and method for connecting peripheral buses through a serial bus

System and method for coupling peripheral buses through a serial bus using a split bridge implementation

An improved data acquisition system for digitizing and storing analog data at a selectable sample rate. The analog data signal is first digitized at a rate defined by a high-frequency clock signal. A decelerator collects every N digital data samples and outputs the samples to N memory partitions at a reduced rate equal to the original clock frequency divided by N. The N memory partitions are further configured to receive N store-enable signals corresponding to each of the N digital data samples. Each of the N store-enable signals determines whether a memory partition will store the corresponding digital data sample. By choosing an appropriate pattern for the N store-enable signals, only a portion of the generated digital data signals is stored in memory. This results in a selectable effective sampling rate for the analog data.

Data acquisition system and method with a selectable sampling rate

An improved system and method for transferring data over a serial bus. Incoming data is stored into data buffers with a dynamically variable size. The size of each data buffer may be adjusted as new data come in. Data with the same originating address are stored in the same data buffer. An arbiter, coupled to the data buffers and to the serial bus, monitors each of the data buffers and the availability of the serial bus. When the serial is available, the arbiter transfers data from one of the data buffers according to some predetermined priority. For example, the largest buffer may have the highest priority. Such an assignment of priority makes very efficient use of the serial bus since larger amounts of data have less overhead and are thus more efficient to transfer. In addition, while data is transferring out of one of the data buffers, data is accumulating in all the other buffers. This makes the other buffers larger and more efficient to transfer upon later availability of the serial bus. The arbiter may also include logic for determining how long it has been since the last time data was transferred out of each data buffer which ensures not starving data in the data buffers.

Arbiter for transferring largest accumulated data block output from data

A system and method for converting VXI block transfer cycles to PCI burst cycles. The present invention may also be generalized to convert between any of various types of buses which use block transfer cycles and burst cycles. A bus bridge or interface unit is coupled between a VXI bus and a PCI bus. The bus bridge includes a VXI to PCI adapter for converting VXI block cycles to PCI burst cycles. The bus bridge includes a buffer which receives VXI block transfer cycles and stores the VXI cycles. The bus bridge also includes control circuitry which tags data in the received VXI block transfer cycles in order to identify and separate different VXI block transfers. Once all the cycles of a given data transfer have been tagged, they are transferred along the PCI bus as a PCI burst cycle.

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Georgetown, TX, United States of America

B Keith Odom