Hyannis Port Research, Inc.

Avid Technology Limited

B Joshua Rosen

Anthony D Amicangioli

Allen Bast

Christophe Juhasz

Eric C Peters

A distributed computing system, such as may be used to implement an electronic trading system, supports a notion of fairness in latency. The system does not favor any particular client. Thus, being connected to a particular access point into the system (such as via a gateway) does not give any particular device an unfair advantage or disadvantage over another. That end is accomplished by precisely controlling latency, that is, the time between when request messages arrive at the system and a time at which corresponding response messages are permitted to leave. The precisely controlled, deterministic latency can be fixed over time, or it can vary according to some predetermined pattern, or vary randomly within a pre-determined range of values.

Highly deterministic latency in a distributed system

Systems and methods are disclosed herein that provide low latency data communication with improved physical link layer reliability through repeated physical layer retransmission of data over a data connection whenever the connection is idle (i.e., no new data to send). In some embodiments, the transmission of administrative control symbols (e.g. 'idles,' “commas”, etc.) can be suppressed or otherwise reduced to allow some of the available connection bandwidth to be used for data redundancy and fault tolerance through the repeated retransmission of data as described in more detail below. Accordingly, instead of executing time-consuming error correcting routines, a receive node can discard the erroneous data frame and process at least one repeat frame that carries the same data payload. Sequence numbers and/or other repeat indicators can be used to distinguish original frames from repeat frames and/or for identifying which frames carry the same data payload.

Systems and methods of low latency data communication for physical link layer reliability

Systems and methods for clock synchronization are disclosed in which a primary node generates special physical layer clock sync symbols from the output of a reference clock and inserts the clock sync symbols within a symbol stream to one or more secondary nodes. Upon receiving a symbol stream, a secondary node can extract the clock sync symbols from the stream to synchronize its local clock with the reference clock of the primary node. In particular, the clock sync symbols can be inserted into the symbol stream at any arbitrary symbol location, e.g., even between consecutive symbols of a symbol encoded data frame. The clock sync symbols can also replace some control symbols in the symbol stream, such as idle or comma symbols. Accordingly, the clock sync symbols can be inserted into a symbol stream at fixed intervals, irregular intervals, or at any arbitrary time for high resolution clock synchronization.

Systems and methods for clock synchronization using special physical layer clock sync symbols

An electronic trading system and corresponding method are based on a point-to-point mesh architecture. The electronic trading system comprises a gateway, core compute node, and sequencer. The core compute node performs an electronic trading matching function. The gateway transmits a message to the core compute node via a first direct connection. The gateway transmits the message via a second direct connection to the sequencer which, in turn, transmits a sequence-marked message to the core compute node via a third direct connection. The core compute node determines relative ordering of the message among other messages in the electronic trading system based on the sequence-marked message to complete the electronic trading matching function, deterministically. The gateway, core compute node, sequencer, and respective direct connections form at least a portion of the point-to-point mesh architecture and enable the electronic trading system to perform high-speed, deterministic, electronic trading of financial instruments while exhibiting low latency, fairness, and fault tolerance, among other features.

Electronic trading system and method based on point-to-point mesh architecture

Systems and methods are disclosed herein that provide low latency data communication with improved physical link layer reliability through repeated physical layer retransmission of data over a data connection whenever the connection is idle (i.e., no new data to send). In some embodiments, the transmission of administrative control symbols (e.g., 'idles,' 'commas', etc.) can be suppressed or otherwise reduced to allow some of the available connection bandwidth to be used for data redundancy and fault tolerance through the repeated retransmission of data as described in more detail below. Accordingly, instead of executing time-consuming, error correcting routines, a receive node can discard the erroneous data frame and process at least one repeat frame that carries the same data payload. Sequence numbers and/or other repeat indicators can be used to distinguish original frames from repeat frames and/or for identifying which frames carry the same data payload.

A distributed computing system, such as may be used to implement an electronic trading system, controls inbound message flow rates. Limiting a per-client or per-connection inbound message rate also helps ensure fair provisioning of computing resources, so that a single client's excessive use of resources cannot overwhelm the system to such an extent that it prevents other clients from interacting with the distributed system. It is also desirable to have system-wide control of the overall inbound message rate across all client connections. Such system-wide control ensures that the distributed system as a whole can maintain the required levels of service, including offering a predictable level of access for all clients.

Local and global quality of service shaper on ingress in a distributed system

An image digitizer including a pixel engine connected to both a video memory and a processor. The pixel engine is configured to enable pixels to be transferred out of memory or read into memory while bypassing the processor thereby allowing more efficient transfer of data into and out of the image digitizer.

Growing community of inventors

Westford, MA, United States of America

B Joshua Rosen