North Carolina State University

B Jayant Baliga

Jacek Korec

Mallikarjunaswamy S Shekar

A gate-controlled bipolar transistor with buried collector includes a wide base bipolar transistor in a semiconductor substrate having a trench at a face thereof. A dual-channel insulated-gate field effect transistor (IGFET) is also included adjacent a sidewall of the trench for providing gated turn-on and turn-off control of the bipolar transistor. The bipolar transistor includes a buried collector region at a bottom of the trench, which is electrically connected to a cathode contact at the face. An emitter of the transistor is electrically connected to an anode contact at an opposing face of the substrate. For turn-on, the base of the bipolar transistor is electrically connected to the cathode contact upon the application of a gate bias signal to the IGFET. By electrically connecting the base to the cathode contact, forward conduction can be established once the anode contact is appropriately biased relative to the cathode contact. Latch-up can also be prevented by using the buried collector region as a diverter region to prevent the regenerative conduction between P--N--P--N coupled regions of the transistor.

Latch-up resistant bipolar transistor with trench IGFET and buried

A semiconductor switching device includes a plurality of adjacent and parallel-connected switching cells in a semiconductor substrate. Each cell includes a thyristor having a floating emitter region and a trench-gate field effect transistor (TFET) for providing turn-on and turn-off control of the thyristor. In one embodiment of the switching device, parasitic thyristor latch-up is suppressed by using a dual-channel TFET which forms both inversion-layer and accumulation-layer channel connections in series between respective floating emitter regions and the cathode contact. In another embodiment, parasitic thyristor latch-up is prevented by joining floating emitter regions of a pair of adjacent cells to thereby eliminate a parasitic P-N-P-N path between the anode and cathode contacts. According to this second embodiment, a dual-channel TFET is preferably used to form a separate first conductivity type inversion-layer channel adjacent a first sidewall of the trench and a second conductivity type inversion-layer channel adjacent a second opposing sidewall of the trench. These channels provide the necessary electrical connections for both gated turn-on and turn-off control.

Dual-channel emitter switched thyristor with trench gate

A trench gate lateral MOSFET structure has the voltage supported along side walls and the bottom surface of the trench. With narrow source and drain mesa regions that are optimally doped, a uniform electric field is obtained vertically in the mesa regions and horizontally at the bottom of the trench, allowing a relative high doping level in an N-drift region resulting in specific on-resistances well below those of conventional lateral MOSFETs at a high breakdown voltage.

Trench gate lateral MOSFET

A switching device including four layers (20), (22), (42) and (44) and a gate electrode (32). In its blocking state the switching device operates as a conventional thyristor. The device is turned off by reducing the effective resistance of the upper base region (42) by applying a negative voltage to the gate (32).

Growing community of inventors

Raleigh, NC, United States of America

B Jayant Baliga