Intel Corporation

Azydee Hamid

Keng Teck Yap

Mahesh U Wagh

Venkatraman Iyer

Zuoguo Wu

Gerald S Pasdast

Lip Khoon Teh

One or more link training signals are received, including instances of a link training pattern, on a plurality of lanes of a physical link that includes at least one valid lane and a plurality of data lanes. The plurality of lanes are trained together using the link training signals to synchronize sampling of the valid lane with sampling of the plurality of data lanes. An active link state is entered and a valid signal received on the valid lane during the active link state. The valid signal includes a signal held at a value for a defined first duration and indicates that data is to be received on the plurality of data lanes in a second defined duration subsequent to the first duration. The data is to be received, during the active link state, on the plurality of data lanes during the second defined duration.

Valid lane training

In some embodiments a functional PCI Express port includes first buffers and an idle PCI Express port includes second buffers. One or more of the second buffers are accessed by the functional PCI Express port. Other embodiments are described and claimed.

Modular scalable PCI-Express implementation

Methods and apparatus for achieving high bus bandwidth transfer using a split data bus. A data bus is split into multiple segments whose access is, individually controlled by an arbitration control unit in a manner that supports concurrent data transfers. Thus, the split data bus is able to concurrently transfer data between multiple master-slave pairs during a given data cycle. A split address but is provided to allow concurrent access requests to be considered for grant. In one embodiment, the data bus includes a read data bus and a write data bus.

Growing community of inventors

Penang, Malaysia

Azydee Hamid