Kabushiki Kaisha Toshiba

Azuma Suzuki

Masataka Matsui

Hiroyuki Hara

Shigeyuki Hayakawa

Mitsuo Isobe

Takayuki Ootani

Hatsuhiro Kato

A semiconductor integrated circuit device includes a first flip-flop circuit receiving data in synchronization with a first clock signal, a logic circuit performing a predetermined process on data output from the first flip-flop circuit, a hold buffer delaying transmission of an output of the logic circuit, a second flip-flop circuit receiving an output of the hold buffer in synchronization with a second clock signal, and a power supply circuit capable of selecting a supply of a power supply voltage to the first flip-flop circuit, the logic circuit, and the second flip-flop circuit between a first power supply voltage and a second power supply voltage higher than the first power supply voltage. A power supply voltage supplied to the hold buffer remains the same when the power supply voltage supplied to the first flip-flop circuit, the logic circuit, and the second flip-flop circuit changes between first and second power supply voltages.

Semiconductor integrated circuit device

A high speed impedance matching circuit suitable for use in high speed semiconductor integrated circuits matches the output impedance of a semiconductor device to the impedance of other devices such a computer system bus thereby reducing signal reflections caused by impedance mismatches and which can adversely affect the operation of a high speed computer system. The impedance of an output buffer is matched to the impedance of an external resistor.

Impedance matching circuit, high speed semiconductor integrated circuit employing the same and computer system employing the integrated circuit

A semiconductor device is equipped with an improved programmable impedance output buffer driver which makes it possible to adjust the impedance of the output buffer of the semiconductor device to the impedance of the bus lines of the system bus in a normal operation mode and to adjust the impedance of the output buffer of the semiconductor device to a predetermined fixed impedance in a test mode. It is therefore possible to effectively and accurately conduct tests of the semiconductor device.

Programmable impedance output buffer drivers, semiconductor devices and

A semiconductor memory has memory cells for data storage, connected to bit line pair a memory cell selection decoder for selecting the memory cell in the plurality of memory cells corresponding to a bit line direction address, a bit line load circuit for supplying a voltage potential to the bit line pair, and an impedance control circuit for receiving the bit line direction address and changing an impedance of the bit line load circuit according to the bit line direction address. The semiconductor memory performs data write-in and data readout operations from/to the memory cell in the plurality of memory cells selected by the memory cell selection decoder through the bit line pair.

Semiconductor memory device for high speed operation

A semiconductor memory device of the present invention is so constituted that, in addition to a first address register for fetching and holding an address signal in synchronous with a clock signal irrespective of read operation and write operation, a second address register is provided to hold a write address, and an address selection circuit selects the held write address to write data held in an input data register into a cell. Thereby, a late write system can be achieved in an synchronous SRAM.

Semiconductor memory device

A synchronous-type memory performing in synchronization with a clock provided from an external device. This memory includes memory cells for storing data and selected by one of word lines, a decoder and a S/A. The decoder latches an address to select a word line in accordance with a rising edge of the clock, selecting a word line, and deselecting all word lines in accordance with a falling edge of the clock. The S/A stores the data transferred from the memory cell belonged to the word line selected by the decoder in synchronism with the rising edge of the clock before all the word lines is switched by the decoder to a deselected state, synchronized with the falling edge of the clock.

Synchronous-type memory

A static random-access memory (SRAM) of late-write type, in which the total time required to write data is reduced, thereby increasing the write margin. No time is therefore wasted in writing and reading data. The SRAM has an address register for holding a write address, besides an address register for holding an input address. A pass gate selects the write address held in the address register or the input address held in the address register. In a read cycle, a decoding path is formed to decode a read address, without using delay circuits. In a write cycle, a second decoding path is formed to decode a write address, using delay circuits. In the cycle preceding the first write cycle coming after the operating mode of the SRAM is switched from the read mode to the write mode, a third decoding path is formed to decode the write-address signal read from the address register. The first, second and third decoding paths are controlled by pass gates.

Late-write type SRAM in which address-decoding time for reading data

Semiconductor memory device with bit line load circuit for high speed

The redundancy circuit device includes a main word line 1 for selecting a first memory area and a subsidiary word line 2, and a spare subsidiary word line 4 for selecting a second memory area (in which spare memory cells are arranged). In case a defective memory cell exists in the first memory cell area, the address is programmed by a redundancy program circuit 14 of a redundancy circuit 41 (provided for each section) of a section decoder 42. Further, when a row partial signal outputted from a row partial decoder 13 hits a defective memory cell, the spare subsidiary word line 4 is selected through the redundancy program circuit 14 to select the spare memory cell, without selecting the subsidiary word line 2. In a memory device of double word line system, a defective memory cell can be replaced with a spare memory cell in unit of each of a plurality of the subsidiary word lines connected to the main word line, thus improving the redundancy efficiency and thereby increasing the production yield of the memory chip.

Redundancy circuit device

A static memory device comprises a memory cell array having of a plurality of sections, each including a plurality of memory cells. A selection signal for selecting one section is generated in accordance with a data writing or reading operation. First and second potentials of high level are generated, and one of the potentials are selectively supplied to pairs of bit lines in one of the plurality of sections. In a data writing operation, the pairs of bit lines are precharged to the first potential, e.g., the supply voltage V.sub.cc, and in a data reading operation, the pair of bit lines is precharged to the second potential, e.g., V.sub.cc -2V.sub.f, where V.sub.f is a forward voltage of a diode.

Static memory device

A static random access memory device is comprised of a write mode detector for detecting a signal state transition of a write enable signal changing to an active state, an input data transition detector for detecting a transition of the input data supplied from exterior, during a continuation of the active state of the write enable signal, an address signal transition detector for detecting a transition of an externally applied address signal during an active state of the write enable signal, a power down timer for generating a pulse signal with a predetermined pulse width in response to any of the detecting signals outputted from the write mode detector, input data transition detector, and address signal transition detector, a gate circuit for permitting the output data from a row decoder to be transferred to memory cells during a period that the power down timer generates a pulse signal, and for inhibiting that data transfer during a period that the power down timer rests, and a write circuit control circuit allowing a write circuit to supply write data to the bit line pair during a period that the power down timer generates a pulse signal, and prohibiting that write data transfer during a period that the power timer rests.

Static random access memory device with power down function

A static random access memory device is comprised of a write mode detector for detecting a signal state transition of a write enable signal changing to an active state, an input data transition detector for detecting a transition of the input data supplied from exterior, during a contamination of the active state of the write enable signal, a power down timer for generating a pulse signal with a predetermined pulse width in response to either of the detecting signals outputted from the write mode detector and input data transition detector, a gate circuit for permitting the output data from a row decoder to be transferred to memory cells during a period that the power down timer generates a pulse signal, and for inhibiting that data transfer during a period that the power down timer rests, and a write circuit control circuit allowing a write circuit to supply write data to the bit line pair during a period that the power down timer generates a pulse signal, and prohibiting that write data transfer during a period that the power timer rests.

A semiconductor memory device comprising a memory cell-selecting section, an input supply control section, and a bit-line potential control section. The memory cell-selecting section includes a row decoder and a first gate circuit coupled to the output thereof. The memory cell-selecting section drives all the memory cells making up the memory device, when it is set in the mode for clearing the memory device, and the input data supply control section disconnects a pair of bit lines from a write circuit when the control section is set in this same mode. When the bit-line potential control section is set in the memory-clearing mode, it sets the potential of one of the bit lines at a high level, and the potential of the other bit line at a low potential.

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Tokyo, Japan

Azuma Suzuki