Samsung Electronics Co., Ltd.

Azmat Raheel

Hyo Jin Kim

Chul Hong Park

Kwan Young Chun

Su Hyeon Kim

Ji Wook Kwon

Su Hyeong Choi

Byung Ju Kang

A layout design system, semiconductor device using the layout design system, and fabricating method thereof are provided. The fabricating method of a semiconductor device includes loading a first layout, wherein the first layout comprises a first active region and a first dummy region, and the first active region comprises a fin-type pattern design having a first width, generating a second layout by substituting the fin-type pattern design with a nanowire structure design and forming a nanowire structure by using the second layout, wherein the second layout comprises a second active region in the same size as the first active region, and a second dummy region in the same size as the first dummy region, the nanowire structure design has a second width greater than the first width, and the nanowire structure comprises a first nanowire extending in a first direction, a second nanowire extending in the first direction and being formed on the first nanowire at a spacing apart from the first nanowire, a gate electrode surrounding a periphery of the first nanowire and extending in a second direction of intersecting with the first direction, a gate spacer being formed on a sidewall of the gate electrode and comprising an inner sidewall and an outer sidewall facing each other, the inner sidewall of the gate spacer facing a side surface of the gate electrode, and a source/drain epitaxial layer on at least one side of the gate electrode and being connected to the first nanowire.

Layout design system, semiconductor device using the layout design system, and fabricating method thereof

Growing community of inventors

Suwon-si, South Korea

Azmat Raheel